Direct wafer bonding

Fig. 15.13 shows a bonding map for silicon wafer bonding combinations of topography and spatial wavelength that fall below the traces will bond those above the traces will produce voids [101]. This and further work by Turner et al. have explored parameters for direct wafer bonding under clamped conditions [107], addressed wafer bow and etch pattern considerations [108], as well as nanoscale roughness considerations [101]. This work shows that... 

Turner K, Spearing S, Baylies W, Robinson M, Smythe R. Effect of nanotopography on direct wafer bonding modeling and measurements. IEEE Trans Semicond Manuf 2005 18 (2) 289-296. 

Turner K, Spearing S. Modeling of direct wafer bonding effect of wafer bow and etch patterns. J Appl Phys 2002 92(12) 7658-7666. 

N. Miki, X. Zhang, R. Khanna, A. A. Ayon, D. Ward, and S. M. Spearing, "Multi-stack silicon-direct wafer bonding for 3D MEMS manufacturing," Sensors Actuators A Physical, 103(1-2) 194-201,2003. 

The low-index layer is perforated by many small ohmic contacts that cover only a small fraction of the entire area. The array of microcontacts allows the electrical current to pass through the dielectric layer. Assuming that the ohmic contacts have an area of 1 % of the reflector, and that the alloyed ohmic contact metal is 50% reflective, the reflectivity of the ODR is reduced by only 0.5%. The ODR described here can be used with low-cost Si substrates or metal substrates using conductive epoxy or a metal-to-metal bonding process. These bonding processes have much less stringent requirements than direct semiconductor-to-semi-conductor wafer bonding processes. 

The fabrication uses the parylene-C wafer bonding technique at a low temperature of 280 °C. Here, an oxygen plasma-treated parylene-C can bond directly to SisN4 with an average bonding strength of 23 MPa. 

In the most fundamental configuration, the semiconductor die is taken directly from the wafer without further processing (generally referred to as a bare die). In this process, the die is mechanically mounted to the substrate with epoxy, solder, or by direct eutectic bonding of the sihcon to the substrate metallization, and the electrical connections are made by bonding small wires from the bonding pads to the appropriate conductor. This is referred to as chip-and-wire technology, illustrated in Fig. 11.10. 

Another important factor is the corrosiveness of the adhesive. This may be especially important in those cases where the PSA has direct contact with the bare wire, the electronic component, or the silicon wafer in a dicing operation. In those cases where an electrical current is running through the device, electrolytic corrosion processes may occur, especially if moisture can penetrate into the adhesive or bond line. 

PhUlips RJ (1990) Micro-channel heat sinks. In Bar-Cohen A, Kraus AD (eds) Advances in thermal modeling of electronic components and systems, vol 2, pp 109-184 Plosl A, Krauter G (1999) Wafer direct bonding tailoring adhesion between brittle materials. Mater Sci Eng R25 92-98... 

Figure 4. Simplified schematic of an optical/infrared focal plane array. The detector is a thin wafer of light sensitive material that is connected to a thin layer of solid state electronics - the connection is made either by direct deposition (CCD) or bump bonding (IR detector). The solid state electronics amplify and read out the charge produced by the incident light.

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