Capacitors parallel switching

Parallel switching of capacitor banks (i) Inrush current... 

Consider the scheme of Example 23.4 having an automatic parallel switching. If we assume the closing sequence cycle to be 30 seconds, the recommended value of discharge resistance for each 20 kVAr capacitor bank having a capacitance of 120 fiF can be determined as follows ... 

We know intuitively (and also from the capacitor equation) what happens to a capacitor when we attempt to suddenly discharge it (by means of the parallel switch). Therefore, we can now easily guess what happens when we suddenly try to discharge the inductor (i.e. force its current to zero by means of the series switch). 

A diode array consists of a series of photodiode/ capacitor parallel circuits positioned side by side on a silicon chip. Each such circuit is connected via its own solid-state switch controlled by a shift register, to a common output line. The shift register is controlled over a quartz oscillator (timer). The readout cycle, corresponding to the illumination time, falls in the 100 ms range. A schematic diagram of the diode array is given in Figure 7. 

Parallel operation of capacitor bank C2 with an already switched capacitor C,... 

If we are able to provide an inductance of this value with each capacitor bank of 60 kVAr the problem of excessive inrush transient current can be overcome and the component ratings as chosen above will be sufficient to switch a parallel circuit. 

In TSCs the thyristors are used in anti-parallel to switch a capacitor bank ON or OFF but without any phase angle control. A TSC therefore does not by itself generate any harmonics, unlike a TCR. 

These cause dynamic issues to the switching power supply, and usually the only solution to that is to have enough bulk capacitance present on the 12V output rail. Luckily, since the main feedback loop is derived from the primary 5V/3.3V rails of the power supply, there is no minimum ESR requirement for the 12V rail output capacitance, and we can freely add several electrolytic capacitors in parallel. However, modern core processors can place very fast transient load demands on the primary regulated rail, too, and for that we need a whole bunch of ceramic capacitors sitting right at the point of load. In that case we must ensure the converter is designed to accept ceramic loads. Otherwise it will break up into oscillations. 

In the buck however, note that though the output diode needs to be positioned close to the IC/switch, the output capacitor is not critical (its current is smoothened by the inductor). If we place a ceramic capacitor in parallel to the output capacitor, it is only for the purpose of decreasing high-frequency noise and ripple at the output even further. But it is really not mandatory, and can cause severe loop instability, particularly with voltage mode control, especially if the effective series resistance (ESR) of the output capacitor section becomes too low (less than 100 inQ typically). 

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