Algorithmic Level Synthesis

This book presents research aimed at providing computer-aided design tools for two higher level steps in the design process Algorithmic Level synthesis and Register-Transfer Level synthesis. 

Computer-aided design tools to support Algorithmic Level synthesis. 

Design entry in a high-level synthesis system is an algorithmic description written in a common programming language (like PASCAL or FORTRAN), or by a special purpose hardware description language (HIX), such as ISPS, DSL or VHDL. 

Eisenbiegler, D., Blumenrohr, C. Kumar, R. (1996), Implementation issues about the embedding of existing high level synthesis algorithms in HOL, in Proc. TPHOL 96 , Turku (Finland), pp. 157-172. 

K, O Brien, M, Rahmouni, and A. Jerraya. DLS a scheduling algorithm for high-level synthesis in VHDL. Proc. Europ. Design Automation Conf., Paris, Prance, Feb 1993. 

M. van Swaaij, J. Rosseel, F. Catthoor, and H. De Man. High-level synthesis of ASIC regular arrays for real-time signal processing systems. In Proc. Int. Workshop on Algorithms and Parallel VLSI Architectures, Pont-a-Mousson, Prance, June 1990. 

D.E. Thomas, E.D. Lagnese, R.A. Walker, J.A. Nestor, J.V. Rajan, and R.L. Blackburn, Algorithmic and Register-Transfer Level Synthesis The System Architect s Workbench, Norwell, MA Kluwer Academic Publishers, 1990. 

Pierre G. Paulin and John P. Knight, Algorithms for High-Level Synthesis , IEEE Design and Test, pages 18-31, December 1989. 

Pierre G. Paulin, High-Level Synthesis of Digital Circuits Using Global Scheduling and Binding Algorithms, PhD Thesis, Dept, of Electronics, Carleton University, January 1988. 

The goal of the System Architect s Workbench project is to do research in the areas of Algorithmic and Register-Transfer Level synthesis, and to develop demonstration design tools to support the research. A diagram of the Workbench is shown in Figure 1-4. 

The research reported here highlights three contrasts in synthesis tool development, namely how to handle the interactions between the Register-Transfer Level synthesis steps, the difference between style-specific and general synthesis, and the means of representing knowledge in the synthesis algorithms. 

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