Algorithmic and RT Level Synthesis

Now that the basic representations for the Workbench synthesis tools have been defined, this section defines the synthesis steps necessary to produce a controller and data path represented at the Register-Transfer level from a behavioral specification at the Algorithmic Level. 

Register-Transfer Level Synthesis includes two phases, control step scheduling and data path allocation and binding. 

One or more control steps are created for each basic block Rj. Each operation Xa in Bi is assigned to either a single control step cs y or a contiguous range of two or more control steps [ csij2 csij2 ] Scheduling affects the outcome of synthesis in several ways. First, it fixes the order and duration of each operator s execution as it is 

A functional unit binding assigns an operation Xa to an allocated functional unit mfh that can perform the operation. Many operations may be bound to the same functional unit if they are not scheduled during the same control step. A functional unit binding includes the creation of a micro-operation that selects the proper function in the proper functional unit. 

Values that need to be stored are called regvals. For regvals, two paths of connection must be established a path from the output of the functional unit bound to to the input of the storage element bound to %l,cl from the output of the same storage element to the input 

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