With Asynchronous Preset and Clear

So far we have talked about synthesizing simple D-type flip-flops. What if we wanted to infer a flip-flop with asynchronous preset and clear To generate such a flip-flop, a special form of if statement has to be used. This is best shown with an example template. 

If negedge B is present in event list, then the if statement starts of as if (IB) 

The statements within each if branch (except the last) represents asynchronous logic, while the statement in the last else branch represents synchronous logic. 

If a variable is assigned a value in any of the asynchronous sections and is also assigned in the synchronous part, that variable will get synthe- 

Here is an example of an up-down counter with asynchronous preset and clear. 

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For the above example, a synthesis tool may alternately not generate a latch with asynchronous preset and clear, but direct the preset clear logic into the D-input of a simple latch. This is shown in the synthesized netlist that appears in Figure 2-43. 

Since NextState is assigned a value under the control of a clock edge (Stmt C) and it is also assigned asynchronously (Stmt A and B), a falling-edge-triggered flip-flop with asynchronous preset and clear is synthesized. This is shown in Figure 2-53. Note that four flip-flops are required. The first flip-flop (the leftmost bit of NextState) has both asynchronous preset and clear terminals since it needs to be preset on Reset and cleared on Set. Similarly, the fourth flip-flop has both asynchronous preset and clear terminals since it needs to be preset on Set and cleared on Reset. The... 

Two flip-flops with asynchronous preset and clear are synthesized for the variable QuickBus. The variable LoadData is connected to the preset clear inputs of the flip-flops through other logic. When PreLoad is active (is 0) and LoadData changes, the outputs of the flip-flops are immediately affected because of the asynchronous data change. However in the design model, any change on LoadData has no effect on the output QuickBus. Thus there is a mismatch. 

A structural style architecture can be used to model sequential circuits. The storage elements used in a sequential circuit are edge-triggered latches - flip flops - or level-triggered latches - transparent latches. These can be instantiated from libraries provided by the synthesis tool or technology vendor. This can limit the flexibility of an implementation as not all vendor technologies will support all types of storage elements. Elements such as flip flops with asynchronous preset and clear inputs, for example, may be omitted from a library. 

The RESET signal is synchronous and is part of the combinational logic input to each flip flop. The circuit behaviour could have been specified as asynchronous by performing the reset sequence outside the clocked part of the process. This would have inferred flip flops with Preset and Clear inputs. The actual construction of a behavioural description to produce this circuit is left for the reader to attempt. Beware, oAer changes will also be required to the process ... 

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