Training a NanoCell

Training a NanoCell in a reasonable amount of time will be critical. Eventually, trained NanoCells will be used to teach other NanoCells. NanoCells will be tiled together on traditional silicon wafers to produce the desired circuitry. We expect to be able to make future NanoCells 0.1 pm2 or smaller if the input/output leads are limited in number, i.e. one on each side of a square. 

Before exploring the optimization problems with the assumption of omnipotence and omniscience, it is worthwhile to ask whether such a problem is of practical use or is merely an academic exercise. This molecular electronics project is currently in the proof-of-concept phase. Before determining whether it is possible to train a NanoCell with realistic constraints, we are attempting to verify whether it is theoretically possible. If it becomes clear that it is impossible to train a randomly assembled NanoCell as a 2-bit adder, even with the assumptions of omnipotence and omniscience, then there is no point in trying to train one without these simplifying assumptions. Hence, the optimization problem with the supposition of omnipotence is of practical use. 

Another potentially advantageous addition to training a NanoCell is connectability . In other words, train a NanoCell so that it is easily connected to other NanoCells. One strategy for doing this is to pick some target such as the overall resistance of a NanoCell. When two NanoCells are hooked together, one looks simply like a resistor to the other. Therefore, if a NanoCell were trained with some resistor hooked to each output and trained for some target resistance, then that NanoCell should be easily wired to another NanoCell with similar overall resistance. 

Although, the problem of omnipotently training a NanoCell has been thoroughly explored in this chapter, there are still some potential improvements that should be explored. In the next section the issue of hooking NanoCells together is addressed. 

The primary factor in determining the functionality of a NanoCell is the I(V) characteristic of the molecule used. Hence, we have found that before beginning to train NanoCells it is essential to first gain an understanding of the particular molecule used. 

Before we began simulating the training of NanoCells, no one knew whether anything useful could be done with a random array of NDR devices. With the NanoCell simulator, we have shown that in fact NanoCells can be trained as fairly complex logical devices with the simplifying assumption of omnipotent training. 

Figure 6.32 This is a NanoCell trained as an inverter. Pin A is set to input, and pin 1" is set to output. The input voltage and output current are displayed, as well.

Figure 6.35 This is a NanoCell trained as four independent NAND gates. The molecules in each comer are on , while others are off . Pins A through H are set to input, and pins 1 through 4 are set to output. Pins A , B and 1 form one independent NAND, etc. The on to off ratio is 15 to 1. If all molecules are on , there are still four NANDs. The on to off is just 2 to 1. Note that this NanoCell looks fairly straightforward to train in a mortal fashion.

Figure 6.45 Depicted here is a NanoCell trained as a half adder connected to a NanoCell trained as a comer turn. The architecture that uses these cells is displayed in Figure 6.36. The input and output signals are shown in Figure 6.46.

In training NanoCells we discovered that occasionally a certain NanoCell would only function as the desired logic gate if the input voltages were applied in a certain order. Suppose we want to train the NanoCell whose output is shown in Figure 6.74 as an inverter. Table 6.9 displays the desired output and actual output for each truth test. Only the fourth test fails. The output should be off but is actually on . Note that if the truths had been applied as off , on , off, then the NanoCell would have tested as an inverter. This is the way NanoCells are currently trained. Each possible truth is tested once, with the exception of the case where every input is off. This case is tested both first and last. However, for some NanoCells this may not be sufficient. Note that in Table 6.9, each output transition is tested. That is, each truth is tested when the output was previously off and when it was previously on . This provides a method for training more robust NanoCells. 

In this section, various areas of future research are discussed. First improvements in training individual NanoCells are covered, and then strategies for hooking NanoCells together are addressed. This is followed by a section on dropping the assumption of omnipotence for more realistic mortal training. The section concludes with the subject of proofs concerning trainability. 

The simplified NanoCell training problem is particularly well suited to genetic algorithms. After presenting the fundamentals of genetic algorithms, a heuristic for solving this optimization problem is presented. 

Figure 6.25 This is a clock NDR used in simulating NanoCell training. The resulting low and high voltages, V/j, and V,n are shown, as well.

It took an average of four generations to train each inverter. The simulation time depends primarily on the number of molecular switches in the NanoCell. To run a generation of 25 individuals it takes approximately 10 sec if there are 10 switches, 25 sec if there are 100 switches, and 250 sec if there are 1000 switches. Hence four generations took about 160 sec on a 800 MHz desktop PC, virtually all of which was simulation time for IsSpice to operate. In actual physical training time we estimate that this would take on the order of 1 msec since the NanoCell and test electronics can operate at a rate of 100... 

Finally, a 1-bit adder has been trained (Figure 6.34) with a 70-nanoparticle, 1000-molecular switch NanoCell, where the molecules exhibit rectifying diode behavior as displayed in Figure 6.7. In Figure 6.34, the pins labeled A are set to the first input, those labeled B are set to the second input, and those labeled C are set to the third input. The output pins are labeled 1 and 2 . High input voltage is set at 1.8 V, while low input voltage is set at 0 V. The output pin is considered off if there is < 50 pA recorded. It... 

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