Simulated Nanocell

The simulated NanoCell is presented in the next section. The precise I(V) curves used in simulations have not always been obtained experimentally. However, in every case, similar behavior has been observed and chemists expect to obtain the curves that are used. 

After choosing a desired truth table, such as NAND or XOR, I/O pins are set to input and output. Some pins may also be set to high rail, low rail or ground, however, these settings are rarely used in the simulations presented here. 

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Figure 6.1 This is a simulated NanoCell with five I/O leads on each side. Within the cell is a planar array of metallic nanoparticles and molecules (dark and light lines). The molecules can be in a high conducting state (dark lines) or a low conducting state (whilte lines).

Figure 6.5 This is the 1(V) curve used most often in simulating NanoCells. The on to off ratio is 1000 1. Such behavior has only been repeatedly obtained experimently at very low temperatures (approximately 60 K), but chemists on the NanoCell project expect to see it at room temperature in the near future.

Figure 6.6 This I(V) curve is also used in simulating NanoCells. Although it was not obtained experimentally, similar behavior has been observed (see Figure 6.7).

Figure 6.25 This is a clock NDR used in simulating NanoCell training. The resulting low and high voltages, V/j, and V,n are shown, as well.

There are still many substantial obstacles to overcome. Large circuits of simulated NanoCells working in concert must be obtained. This achievement should be realized shortly, however. In addition, results seen in simulation should be validated by tests on physical NanoCells. Simulations should be adapted to reflect what is seen in these experimental cells. After obtaining working physical NanoCells, the issues of size and power must be addressed. What kind of size advantage is possible with a NanoCell What kind of power is required to run a chip of many thousands of the cells Here bistable latches may prove a liability as they draw constant current. 

For the last two years our lab has focused on the NanoCell approach to molecular computing. We have shown via computer simulation that it is possible to program an assembled NanoCell.72 The NanoCell is illustrated in Figure 5.14. 

Once the physical topology of the self-assembly is formed in the NanoCell, it remains static there is no molecule or nanoparticle dynamic character (other than bond rotations or vibrations) to the highly crosslinked network. The only changeable behavior is in the molecular states conducting ON or non-conducting OFF, as set by voltage pulses from the periphery of the cell, or as defined by the search algorithms in these simulations. 

Molecular Dynamics Simulations of a Molecular Electronics Device The NanoCell (.J. Seminario, P. Derosa, L. Cordova B. Bozard)... 

Figure 6.22 The input voltage (top) and output current (bottom) are displayed for a I-molecule inverter (see Figure 6.21). Note that when the input is high, the output is low, and vice versa. The current spikes are due to simulation issues and would not occur in an actual NanoCell.

We further experimented with training NanoCells using another Monte-Carlo search algorithm, simulated annealing. Simulated annealing produced essentially the same results as the GA. It is our opinion that in this case, the particular base search algorithm is not nearly as important as the manner in which it is adapted to the NanoCell problem. 

Before we began simulating the training of NanoCells, no one knew whether anything useful could be done with a random array of NDR devices. With the NanoCell simulator, we have shown that in fact NanoCells can be trained as fairly complex logical devices with the simplifying assumption of omnipotent training. 

In this section the results of the simulated training of voltage in -current out NanoCells are presented. Using this design, several complex, negating logic gates were trained, many of them easily. Except for the four NANDs and the 1 -bit adder, all of these NanoCells were trained with the version of the simulator that worked with IsSpice. 

Inverters, NAND gates, half-adders and 1-bit adders have been found using the NanoCell simulator. For the inverters, NANDS, and half-adders, the simulated I(V) curve displayed in Figure 6.2 was used to characterize the on and off states of the molecular switches. A simulated I(V) curve with rectifying diode behavior was used for the 1-bit adder. 

It took an average of four generations to train each inverter. The simulation time depends primarily on the number of molecular switches in the NanoCell. To run a generation of 25 individuals it takes approximately 10 sec if there are 10 switches, 25 sec if there are 100 switches, and 250 sec if there are 1000 switches. Hence four generations took about 160 sec on a 800 MHz desktop PC, virtually all of which was simulation time for IsSpice to operate. In actual physical training time we estimate that this would take on the order of 1 msec since the NanoCell and test electronics can operate at a rate of 100... 

Clearly if an Eulerian circuit in G is given, then applying the truth tests in the order of the input nodes in the circuit (with the first input node tested first and last) will result in the testing of every output transition. The vast majority of NanoCell training time is spent simulating the circuit in HSpice, so it is important to determine how many truth tests are necessary to test every output transition. Once again, let 2" be the number of truth tests, let p be the number of distinct outputs and let r, be the number of input nodes that... 

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