Nanocell Training

The NanoCell training problem as stated is extremely difficult. We are just now beginning to make progress on this problem using neuro-dynamic programming. These initial results are encouraging, but before attacking this 

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The simplified NanoCell training problem is particularly well suited to genetic algorithms. After presenting the fundamentals of genetic algorithms, a heuristic for solving this optimization problem is presented. 

Figure 6.25 This is a clock NDR used in simulating NanoCell training. The resulting low and high voltages, V/j, and V,n are shown, as well.

In adapting the GA to the NanoCell training problem, the fitness function is the most difficult issue. First consider the voltage in - current out setup. Recall that Iql and Iqh denote the high and low output current thresholds. 

Figure 6.32 This is a NanoCell trained as an inverter. Pin A is set to input, and pin 1" is set to output. The input voltage and output current are displayed, as well.

Figure 6.35 This is a NanoCell trained as four independent NAND gates. The molecules in each comer are on , while others are off . Pins A through H are set to input, and pins 1 through 4 are set to output. Pins A , B and 1 form one independent NAND, etc. The on to off ratio is 15 to 1. If all molecules are on , there are still four NANDs. The on to off is just 2 to 1. Note that this NanoCell looks fairly straightforward to train in a mortal fashion.

Figure 6.38 This is a 20 pin NanoCell trained as an XOR gate. Pins A and B are set to input, and pin Out is set to output. Input voltages and output current and voltage are shown. The dotted line is the clock voltage for the bistable latch.

Figure 6.42 This is a 4 pin NanoCell trained as a half adder. Pins In 0 and In 1 are set to input, and pins OutClk 0 and OutClk 1 are set to output. Output currents and voltages are shown.

Figure 6.45 Depicted here is a NanoCell trained as a half adder connected to a NanoCell trained as a comer turn. The architecture that uses these cells is displayed in Figure 6.36. The input and output signals are shown in Figure 6.46.

Clearly if an Eulerian circuit in G is given, then applying the truth tests in the order of the input nodes in the circuit (with the first input node tested first and last) will result in the testing of every output transition. The vast majority of NanoCell training time is spent simulating the circuit in HSpice, so it is important to determine how many truth tests are necessary to test every output transition. Once again, let 2" be the number of truth tests, let p be the number of distinct outputs and let r, be the number of input nodes that... 

The output transitions algorithm is not something that we currently use in NanoCell training because of the significant increase it would cause in training time. However, in the future we may use the algorithm to evaluate the robustness of trained NanoCells. Nanocells that do not perform the desired logic for every output transition would then be trained further. 

The NanoCell training to date has been conducted under the assumption of omnipotence. However, NanoCells will be trained in a mortal fashion, so it is essential that mortal techniques be investigated in the near future. This is an issue that we are exploring. 

In previous sections, NanoCell training proofs were presented. In this section, some possible methods for improving these results are explored. First, the results are for voltage in - current out NanoCells, and NanoCells will actually be voltage out. Therefore, the results should be adapted to this case. This will be extremely simple if the voltage in - current out observations hold for voltage in - voltage out with the new bistable latches. 

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