Threshold devices gate dielectric

In the standard metal-oxide semiconductor field-effect transistor (MOSFET) drain-current equations, is a proportionality factor that relates the drain current /p, to the gate and drain voltages and V[)s, respectively the threshold voltage V, the channel width W and length L and the gate dielectric capacitance per unit area Cox. The standard drain-current equation for an -channel device in the linear region of operation - V) is [4]... 

FIGURE 6.4.8 (See color insert following page 468.) Threshold voltage and mobility uniformity maps for a 1- x 1-cm 200-OTFT array using pentacene devices with a SiOj gate dielectric. 

Fig. 6.1. A schematic showing the structure and regions of operation of a NMOS c-Si FET. The voltages shown are for illustration only. When Vas exceeds the threshold voltage and Vds is small the channel is inverted at both sides with approximately the same Q and the device behaves as a resistor. When a substantial Vns is applied, the field induced by the gate is partially canceled on the drain end. When the potential at the drain end drops below Vr, Q 0 and the carrier velocity increases to compensate, which leads to pinch-off and a saturation of the transistor characteristic. The carriers are all physically located very close to the gate dielectric interface, the triangle is illustrating that the carrier density is not constant. Since the current flow is constant across the length of the channel, the velocity and lateral field in saturation are not uniform.

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