Synchronous section Process statement

Unlike the Wait statement, the If does not have to be the first statement in the process. This allows both a synchronous section and combinational logic - a combinational section - to exist in the same process. The example below illustrates this (and assumes that all the signals have been declared in the surrounding architecture). 

A signal assigned in one synchronous section cannot be assigned again in any other synchronous section, either in the same or a different Process statement. 

This section has illustrated the important part that the Process statement plays in the design of sequential logic. In Chapter 4, its function in combinational design was also shown. It is good design practice to separate combinational and synchronous sections by using different processes. Box 5.1 offers some guidelines on how to use the process statement and illustrates its syntax. 

A process that contains a Walt statement is a template for a fully synchronous section of an architecture. The clarity of the code is often better than when If statements are used. The following syntax is required ... 

The architecture BADJK, uses two signals to store the present states of the flip flops inverted and non-inverted outputs, SBAR and S. The Case statement inside the S3mchronous section is used to determine the new state of S and assign its value. The value of S is then passed on to SBAR at the end of the Case statement. Unfortunately, the new state is not registered on the flip flop inferred for S until the end of the process so the SBAR will be assigned the old state of S. If this is not bad enough, because SBAR is assigned inside the synchronous section, it also infers another flip flop ... 

The semantics of parallelism is also the same in both VHDL and VHDL-AMS (only processes can legally be placed in parallel, but for completeness we give a hypothetical semantics to parallelism at the statement level too). We have shown in Section 2 that models in both languages are composed of the synchronous parallel composition of models for the individual processes which communicate on the signal (and quantity) states and the simulation time. Intersection of relations is therefore an adequate representation ... 

The SYNC WAIT architecture demonstrated how a Walt statement can be used to infer a sequential section. The whole process must be synchronous and therefore only s)mchronous initialization is possible with a Wait statement. The drcuit produced by this form of sequential logic template is... 

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