Superscalar processors

Regarding related work, we first take a short look on checkpoint mechanisms known from distributed systems. After that, we review related work regarding checkpointing and rollback- and roll-forward procedures in speculative superscalar processors. The influence of different checkpoint lengths onto dependability was examined by Ziv [10]. A central statement is that shorter checkpoint intervals increase dependability, since the probability that faults will propagate will decrease. In case of a fault less work must be thrown away and the amount of data that has to be transferred is reduced [1]. With smaller checkpoint intervals performance degradation occurs. As a consequence, the checkpoint memory can be reduced in size and fault recovery started earlier. Ziv [10] proposes... 

For a rollback of architecturally non-fixed states, mechanisms like the rollback of speculative states within a superscalar processor can be used. The main difference to our work is that the cause and the time of a checkpoint are determined by speculative execution. The cause and occurrence in time of a fault are non-determined. Some methods try to recreate a valid processor state from the reorder buffer [5] [8]. The checkpoint repair method of Hwu and Patt [2] introduces different logical memory ranges on a processor, which consist of a complete register file and additional memory. A dedicated memory is reserved for the actual state. Others hold backup-copies of previous states. If a checkpoint is saved, the actual state is moved in the backup memory. A retry is done via loading of the contents of the backup register file. The method is costly, since multiple cycles are used for the moving of data between backup and architectural register file. The history buffer in the Motorola 88110... 

Schedulability analysis are based on the assumption that the execution time of each task can be accurately estimated. Measurement is always difficult, because, with effects like cache misses, pipelined and superscalar processor architectures, the execution time is highly unpredictable. Run-time monitoring of processor usage permits detecting and responding to wrong estimations in a controlled marmer. 

We do performance evaluations using the sim-outorder simulator, which is the most complicated and detailed simulator in SimpleScalar. In this simulator, timing statistics are generated for a very detailed out-of-order issue superscalar processor core with a two-level cache hierarchy, which is appropriate for performance evaluations. 

Oh, N., Shirvani, P.P., et al. Error detection by duplicated instructions in superscalar processors. IEEE Trans, on Reliability 51(1), 63-75 (2002)... 

Pentium The Pentium represents the evolution of the 80486 family of microprocessors and adds several notable features, including 8K instruction code and data caches, built-in floating-point processor and memory management unit, as well as a superscalar design and dual pipelining that allow the Pentium to execute more than one instruction per clock cycle. 

Pipelining A microarchitecture technique that divides the execution of an instruction into sequential steps. Pipelined CPUs have multiple instructions executing at the same time but at different stages in the machine. Or, the act of sending out an address before the data is actually needed. Superscalar Capable of executing multiple instructions in a given clock cycle. For example, the Pentium processor has two execution pipes (U and V) so it is superscalar level 2. The Pentium Pro processor can dispatch and retire three instructions per clock so it is superscalar level 3. 

Superscalar architecture of the P5-x86 next generation processor. 1992. Hot Chips TV. 

Superscalar This implementation of the processor provides more than one pipeline. As a result, multiple instructions may be at the same stage in their instruction cycle. A superpipeline and a superscalar implementation may exist within the same processor. 

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