Solderability Testing Surface finishes

After 3 years of development, including 2 years of practical testing in the industry up to a commercial scale, we can report (text written in 1998) an interesting new application the preparation of the surface finish of printed circuit boards. The places where the diodes, resistors, etc., have to be mounted and connected to copper-based printed circuits have to be solderable for a period of at least 1 year in... 

Refer to Chap. 42 for detailed information on solderability of PCB surface finishes. Testing methods are contained in the comprehensive joint industry specification ANSI/IPC J-STD 003. Surface finishes are commonly tested in production at the board fabricator using a solder float or solder dip method. When qualifying the finish, an OEM or assembler uses more equipment-specific tests such as wetting balance, rotary dip, or paste spread methods. Solderability should be consistent from day to day and lot to lot, with very little degradation after exposure to at least three assembly thermal exposures. 

It is very important that the solderability test, including any stressing that may be imparted on the deposit, be representative of the failure mode that the surface finish finally succumbs to naturally over time.The use of steam to stress a deposit other than a lead-bearing one is not to be used the recommended stressing is eight hours of exposure to 72°C/85 percent R.H. 

PCB Surface Finishes and Solderability Testing for Plated Through Holes... 

Certain no-clean fluxes are not compatible with each other. Their chemical interaction could result in corrosion on the PCA. To avoid corrosion issues, solder paste flux, wave solder flux, and repair flux should be tested separately and in combination for SIR and ECM with the board surface finish. 

In addition to speed, a number of other factors could impact the fracture strength of solder joints, including surface finish, pad size, ball diameter, ball metallurgy, and pad construction. All these need to be taken into account when comparing ball shear data across different packages. Another important factor that could impact the force-to-failure and the failure modes induced is the time after reflow. It is preferable to perform the test as early as possible after reflow. ... 

Nakamura, Tomoko, Miyamoto, Yoshimasa, Hosoi, Yoshihiro, and Newman, Keith, Solder Joint Integrity of Various Surface Finished Build-Up Flip Chip Packages by 4-Point Monotonic Bending Test, Electronics Packaging Technology Conference,2005,pp. 465 70. 

There appears to be no across-the-board effect of Pb contamination on the TMF of Sn-Ag-Cu solder joints. The sensitivity of Pb-free solder joints to Pb contamination from the component 1/Os was package dependent. That dependence may reflect different quantities of Pb introduced into the joint or the variation in stress state caused by the I/O configuration. There was also an effect generated by the surface finishes (Ni-Au, immersion Ag, etc.) on the circuit board. The TMF tests were performed under the - 55 to 125 °C (-67 to 257 °F) or -40 to 125 °C (-40 to 257 °F) temperature range. 

For large boards, excessive board flexure, during PWB manufacturing, testing, assembly, and use, often can cause solder interconnect failures. Establishment of the strain rate-strain limit for lead-free solder interconnection on different PWB surface finishes can greatly help safeguard the reliability of the products (Ref 23). 

The surface finishes selected were Immersion Silver, Immersion Tin, two HASL (lead-free) and four Organic Surface Protections (OSPs). Four solder alloys were planned for testing, but two were eliminated due to cost, leaving SACX and Sn/Cu/Ni. Five fluxes were evaluated, two of which were chosen because they were commonly used in other experiments. 

FIG. 7 The initial test vehicle used for the evaluation of solders in surface mount applications. It is FR-4,119x162 xO.8 mm. It contains a wide array of component types such as QFPs, at pitches 0.5 and 0.65 mm, 1005, 1608, and 2125 R/C, mini TR/SOT, SOPs, SOJs, crystal/oscUlators, A1 Caps, connectors, and so on. Electrode finishes used were Sn, Sn-Bi, Pd, Sn-Pb, Au, and Ag. (From Ref 15.)... 

FIG. 8 The effect of surface finish on the maximum loads measured during pull tests conducted on SOIC device leads soldered with several Pb-free solders and eutectic Sn-Pb. 

TABLE 11 Component Surface Finishes in Surface Mount Solderability Test Vehicle (STV-SM)... 

On the RTV-SM assembly, component location and position had a strong effect on time-to-first-failure for PLCC-84 and LCCC-44 devices. While there was a wide range of performance exhibited across the eight solder alloys, a similarly wide variation in performance was observed among the various component sites on the same board. Furthermore, a wide variation in performance was also observed at all locations across the three replicate boards used to test each solder. It was concluded that this position effect, coupled with general data variability, overshadowed the effect attributable to the solder alloy alone, and masked the ability to distinguish one solder alloy from any other. None of the Pb-free alloys exhibited catastrophic failure or distinguishably poorer performance than the other Pb-free alloys or the eutectic Sn-Pb control. Component type determined the failure time and mode. There were no clear differences between solder alloys or PWB surface finishes under the vibration conditions studied. 

Organic-coated copper provides a consistent, flat, solderable metal finish. Exposed copper after printed circuit assembly has been a persistent reUabiUty concern, because it is generally not permitted on HASL boards. While exposed Cu on HASL boards is associated with poor solderabUity, which may be due to contaminants that were not removed before the HASL process, there is little evidence that exposed Cu on a properly processed OCC board causes reliability problems. Surface insulation resistance (SIR) testing shows that OCC boards have comparable or better performance than HASL boards in high-temperature, high-humidity storage tests. 

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