Silicon wafer, contamination

Figure 9 Secondary electron image (upper left) and Auger elemental maps of C, Al, Si, and F of silicon wafer contamination comprising an Al central particle with fluorocarbon petals. (Reproduced with permission of ULVAC-PHI.)...

Multielement analysis, excellent detection limits for heavy metals quantitative measurement of heavy-metal trace contamination on silicon wafers... 

Vapor-phase decomposition and collection (Figs 4.16 to 4.18) is a standardized method of silicon wafer surface analysis [4.11]. The native oxide on wafer surfaces readily reacts with isothermally distilled HF vapor and forms small droplets on the hydrophobic wafer surface at room temperature [4.66]. These small droplets can be collected with a scanning droplet. The scanned, accumulated droplets finally contain all dissolved contamination in the scanning droplet. It must be dried on a concentrated spot (diameter approximately 150 pm) and measured against the blank droplet residue of the scanning solution [4.67-4.69]. VPD-TXRF has been carefully evaluated against standardized surface analytical methods. The user is advised to use reliable reference materials [4.70-4.72]. 

Fig. 5. Hydrogen depth profile of a deuterated polystyrene PS(D) film deposited on a protonated polystyrene PS(H) film on top of a silicon wafer as obtained by l5N-nuclear reaction analysis ( 5N-NRA). The small hydrogen peak at the surface is due to contamination (probably water) of the surface. The sharp interface between PS(D) and PS(H) is smeared by the experimental resolution (approx. 10 nm at a depth of 80 nm) [57], The solid line is a guide for the eye...

In some cases, the parts to be coated (such as semiconductor silicon wafers) are stacked vertically. This minimizes particle contamination and considerably increases the loading capacity (as opposed to horizontal loading). 

HIBS is the same as RBS, except that heavy ions are used instead of He++. It is an ion beam analysis tool patented by the Sandia Corporation of the USA, and was developed to enable the measurement of trace levels of surface contamination on silicon wafers. Metal contamination present in starting material is detrimental to devices, since it results in defects which limit wafer yields and impair circuit operation. 

Manufacturing processes are well developed for silicon wafers. To avoid particle contamination, compact clusters of processing units operate in 100-level clean rooms, which for small companies are often rented in larger complexes at approximately 400/ft2-yr. 

All standard cleaning processes for silicon wafers are performed in water-based solutions, with the exception of acetone or (isopropyl alcohol, IPA) treatments, which are mainly used to remove resist or other organic contaminants. The most common cleaning procedure for silicon wafers in electronic device manufacturing is the deionized (DI) water rinse. This and other common cleaning solutions for silicon, such as the SCI, the SC2 [Kel], the SPM [Ko7] and the HF dip do remove silicon from the wafer surface, but at very low rates. The etch rate of a cleaning solution is usually well below 1 nm min-1. 

Contamination of silicon wafers by heavy metals is a major cause of low yields in the manufacture of electronic devices. Concentrations in the order of 1011 cm-3 [Ha2] are sufficient to affect the device performance, because impurity atoms constitute recombination centers for minority carriers and thereby reduce their lifetime [Scl7]. In addition, precipitates caused by contaminants may affect gate oxide quality. Note that a contamination of 1011 cnT3 corresponds to a pinhead of iron (1 mm3) dissolved in a swimming pool of silicon (850 m3). Such minute contamination levels are far below the detection limit of the standard analytical techniques used in chemistry. The best way to detect such traces of contaminants is to measure the induced change in electronic properties itself, such as the oxide defect density or the minority carrier lifetime, respectively diffusion length. 

Polishing uses abrasive compounds and mechanical action to remove contaminants. Although used extensively in preparing glass substrates for chromium masks and in obtaining the desired flatness of silicon wafers, it is seldom, if ever, used once the silicon wafer enters a process sequence. 

A chip-based nanospray interface between an HPLC and the MS has been introduced by Advion Biosystems (Ithaca, NY). This instrument aligns a specialized pipette tip with a microfabricated nozzle, set in an arrayed pattern on a silicon wafer. The advantage of this interface is that each sample is sprayed through a new nozzle, thus virtually eliminating cross contamination. 

Proximity printing, a variation of contact printing, preserves a minimum gap of approximately 10-30 xm between the silicon wafer and the mask. Although the problem of particulate contamination is avoided, light distortion is enhanced, and a loss in resolution results. 

The presence of organic contaminants as small as 1 /tm or films as thin as 1 /rm on silicon wafers during the manufacturing process of integrated circuits can be readily identified (38). These contaminants can affect the performance of the device and must be identified. Figure 3-8 shows the identification of possible Teflon contaminants. Other techniques, such as IR, X-ray diffraction, Auger and electron microprobe, are insensitive in identifying the nature of the contaminant. 

Figure 3-8 Raman microprobe spectrum of fluorinated hydrocarbon contaminant on silicon wafer that had been polished and plasma-etched (lower) and Raman spectrum of polytetrafluoro-ethylene (upper). Laser, 135 mW at 514.5 nm. Slits, 300 jon. Time, 0.5 s per data point. (Reproduced with permission from Adar, F., in Microelectronics Processing Inorganic Materials Characterization (L. A. Casper, ed.), ACS Symposium Series Vol. 295, pp. 230-239. American Chemical Society, Washington, D.C., 1986. Copyright 1986 American Chemical Society.)...

In the semiconductor industries, a number of materials are deposited on silicon wafers using CVD technologies such as plasma-CVD and thermal-CVD as described in the previous section. As the CVD process is repeated, a thick film is inevitably deposited on the various parts of the chamber and the internal walls of the exhaust tubes. This thick film generates contamination particles that affect the electrical resistance of the devices. Accordingly, cleaning of the apparatus is periodically necessary to eliminate the deposits and to improve the reliability of the device. 

F. Sugimoto and S. Okamura, Adsorption behavior of organic contaminants on a silicon wafer surface, J. Electrochem. Soc. 46, 2725, 1981. 

E. Hsu, H. G. Parks, R. Craigin, S. Tomooka, J. S. Ramberg, and R. K. Lowry, Deposition characteristics of metal contaminants from HF-based process solutions onto silicon wafer surfaces, J. Electrochem. Soc. 139, 3659, 1992. 

O. J. Anttila and M. V. Tilli, Metal contamination removal on silicon wafers using dilute acidic solutions, J. Electrochem. Soc. 139, 1751, 1992. 

LI. Suni, G. W. Gale, and A. A. Busnaina, Dissolution kinetics for atomic, molecular, and ionic contamination from silicon wafers during aqueous processing, J. Electrochem. Soc. 146(9), 3522, 1999. 

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