Signal assignment Process statement

If you do not have the next state <= current state statement in the combinational process statement, DC will infer latches for the next state signal. In general, when using a case statement, one must cover all the possibilities or, in other words, assign the next state under all conditions. 

Updating the value of a signal must be performed with care. A signal assignment statement only schedules the update for some unspecified time in the future. This is different to a variable assignment statement, which ensures that the update is effective immediately. It is very important to appreciate this difference, especially when making assignments within processes. 

A conditional signal assignment statement is similar to an If-Else statement. The former is executed concurrently and the latter sequential (inside a process). 

A signal assigned in one synchronous section cannot be assigned again in any other synchronous section, either in the same or a different Process statement. 

Any combinational logic associated with the design must be placed in a separate process or be implemented using concurrent signal assignment statements. 

The fully synchronous process triggers on a falling-edge clock signal. If the reset signal PC is not active, the new state of S is then determined within the Case statement. The new state of S is used to update the outputs Q and QBAR in concurrent signal assignment statements that precede the process. Remember that the order of concurrent statements is irrelevant to their order of execution. 

A function is very similar to a Process statement in its operation except that it cannot contain signal assignment or Wait statements. This means that a function caimot be used to create sequential logic. As the RIPPLE functions illustrate, variables that are local to the function can be declared in the declarative part and its execution is sequential. All objects declared locally are discarded when the final result is returned. The s)mtax of a function and other important details are given in Box 6.4. 

When a branch condition is satisfied in the architecture CASEI, one of the input signals A, B, C or D is assigned directly to Y. In the architectures of Figure 4.6, two alternative method of assigning the output are demonstrated. In CASE2, a variable, TEMP, of type BIT has been declared. A private (non-shared) variable, declared within the process declarative part, is always local to the process. The value stored in TEMP after the Case statement has been evaluated must be assigned to Y inside die process. TEMP cannot be passed out of the process or accessed by any odier concurrent statement, such as another process. If the variable was shared (Qiapter 3)... 

Avoid multiple assignments to one signal within a process, unless each occurs on separate branches of a conditional statement, such as an If-Etse or a Case. 

The architecture BADJK, uses two signals to store the present states of the flip flops inverted and non-inverted outputs, SBAR and S. The Case statement inside the S3mchronous section is used to determine the new state of S and assign its value. The value of S is then passed on to SBAR at the end of the Case statement. Unfortunately, the new state is not registered on the flip flop inferred for S until the end of the process so the SBAR will be assigned the old state of S. If this is not bad enough, because SBAR is assigned inside the synchronous section, it also infers another flip flop ... 

The process STATE SELECT has the sole task of selecting the new state on each dodc cyde. The external reset signal is first tested before the nested Case statements evaluate the new state from die present state and the inputs. As with examples in previous chapters, the external signal is not directly given a new value, but is assigned to a variable called NEXTSTATE. After die new state has been determined the final statement in the process then reassigns the variable to the signal. 

---