Several archetypical process flows and variants

During processing there are a number of opportunities to create shallow states in the semiconductor which can degrade the device transconductance and shift the threshold voltage through the formation of a charged interface dipoles or bulk trap states and release of mobile charges. 

Several archetypical process flows are shown here, primarily based on processes in the literature. All of these provide independent patterning on four layers. A virtually infinite variety of processes can be imagined which combine these or other unit operations, depending on the desired device characteristics, required circuit topography, available equipment, etc. Chapter B provides some tested recipes which can be used as a starting point for development of processes based on a subset of these unit operations. 

For the sake of consistency, the four basic OFET layers will be referred to as the gate layer, gate dielectric layer, source/drain layer, and active layer. OFETs with integrated devices may also re-use one of these four layers for hybrid device integration or introduce additional layers for connectivity or other active device formation. The position of these layers is shown in two idealized OFET cross sections in Fig. 4.12. 

The gate layer (which is also typically used for some interconnect) is a conductor and is patterned both to establish interconnects and decrease the overlap capacitance with the source/drain layer which is a drag on performance in many applications. The gate layer is typically the best bonded to the substrate and is often also used to anchor layers that will be used for external connection (e.g. through heat seal connectors or wire bonding). The gate dielectric layer is typically patterned to allow interconnection between 

Semiconductor Drain Gate dielectric Gate Substrate 

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