Sequencing Graph and Resource Model

Similar models are used in existing high-level synthesis systems. They include DACON in Flamel [Tri87], YIF in YSC [BCM+88], sequence, data-flow, and control graphs in the Caddy system [CR89], Value Trace in CMU s System Architect s Workbench [TDW+90], and CDFG in Elf [GK84]. 

This chapter is organized as follows. Section 4.1 describes the semantics of the sequencing graph model. Section 4.2 describes the derivation of a constraint graph model from a sequencing graph model under timing constraints. 

Section 4.3 describes the model of hardware resources used in synthesis. Section 4.4 summarizes the major features of the sequencing graph model. 

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In traditional approaches, two vertices are disjoint if they are scheduled into different control steps. However, since our model supports data-dependent delay operations, these approaches cannot be used in general. Assume all operations have unbounded execution delay, then two operations are compatible if they have the same resource type and are joined by a directed path in the sequencing graph. 

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