Semiconductor wafers, etching

The fabrication method generates functional elements via anisotropic etching of high-quality semiconductor wafers, referred to as mother wafers.13 17 25 The process begins with photolithographic definition of patterns... 

Electrochemical properties of silicon single crystals, usually cuts of semiconductor wafers, have to be considered under two distinct respects (1) As an electrode, silicon is a source of charge carriers, electrons or positive holes, involved in electrochemical reactions, and whose surface concentration is a determining parameter for the rate of charge transfer. (2) As a chemical element, silicon material is also involved in redox transformations such as electroless deposition, oxide generation, and anodic etching, or corrosion processes. 

After the detail study through a thorough process qualification, the new boron carbide coated chamber wall is used to replace the previously anodized aluminum surface. The new ceramic material such as YAG or Y2O3 is used to replace original high purity alumina. This configuration was introduced to semiconductor wafer fabrication for evaluation. Excellent etch performance, enhanced defect and particle reduction, and 50 to 100 times chamber lifetime improvement are reported. The production yield of the wafer fabrication also improved about 7% in production at the customer site (see Fig.l9) [41]. The following data provide some of the information. The sequence of the data collection is as follows ... 

The revolutionary chamber materials study under high density plasma has opened a new scientific field in the characterization of materials. Meeting the comprehensive requirements of plasma etching tools in semiconductor wafer fabrication with the technology node shrinkage is not an easy task. The efforts and methodology developed through these studies have built up the foimdation in the advanced materials characterization, development and application. 

Etching kinetics of semiconductors may be diffusion-controlled in two ways (24). In the first case, the reduction reaction is diffusion limited and controls the etching kinetics. Under these conditions a well defined crystallographic facet is obtained. This behavior is observed at low pH. In the second case of high pH, the rate of anodic dissolution of the semiconductor wafer depends on the mass transport of OH ions to the electrode. Electroless etching based on this limitation shows rounded profiles typical of diffusion-controlled dissolution. 

According to the international technology roadmap for semiconductors, chips with a wafer diameter of450 mm and a feature size of 0.05 /xm by 2011 will serve to decrease manufacturing costs [29]. In the integrated circuit (IC) manufacture process as shown in Fig. 21 [30], dielectric stacks have been formed by the ion etching on the coating of dielectric material formed on the silicon surface (Fig. 21 (a)). 

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