Pixel circuits designs

Knowing /data operational limits during select and deselect times, it is important that the pixel electrode circuit parameters are carefully designed to balance those two limits and to achieve largest possible /data operational range. 

The design of active-matrix TFT (AM-TFT) backplanes for capacitive media, such as electrophoretic ink, has been extensively reviewed [1] and we discuss here some of the most relevant issues for printed backplanes. A simplified equivalent circuit for a pixel in an AM-TFT backplane is shown in Fig. 11.14. 

Although the data here show we can achieve relatively uniform TFT performance, it is still not good enough for a display application, so a compensation circuit would be needed in the pixel design. Threshold voltage stability and uniformity, together, form perhaps the most risky feature of organic TFT backplanes for OLEDs. 

Producing the appropriate alternating-polarity data signals is the responsibility of the display driver circuits. However, the pixel designer must reckon with the fact that data voltages will have alternating polarities and must consider any DC component that may be contributed by the pixel design. 

Aerts, W.E., Verlaak, S., and Heremans, R, Design of an organic pixel addressing circuit for an active-matrix OLED display, IEEE Trans. Electron Devices, 49, 2124,... 

Level 5 (genius) pixels (thousands of transistors) have complexities, in general, above a thousand active devices, a level of complexity sufficient for implementing application-specific integrated circuits (ASICs) and microprocessors. But this functionality level has problems not faced by the lower levels. First, for free-space optical interconnection, optical I/Os should be arranged in a structured two-dimensional pattern in order to effectively use the two-dimensional nature of imaging optics. On the other hand, computer-aided design (CAD) tools for elec-... 

The data push pixel and a number of related analog circuits will be submitted to MOSIS in early June, 1993 for production of a test chip by mid-July. The design of these test chips was guided both by simulation and by experience gained in previous work on the Hughes CHIP 5 array, a 32 x 64 array of time tagging pixels. The size of the pixel is 30 //m (in the 2 direction) x 135 /mi. 

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