Inferring cells using procedure calls

A common complaint in the design community is a lack of control over the cells inferred during synthesis. A combination of procedure (function) calls and DC directives such as the map Jo cntity directive can give the user a fair amount of control over the cells inferred. This helps tackle the issue discussed in Scenario 1 in section 10.1. 

Example 10.3 shows how one can achieve the required functionality via a procedure call. The procedure latch proc is defined in package my pack. This package is analyzed into the work library. When a procedure call to latch proc is made in the VHDL code, the map to cntity directive in the procedure latch proc ensures that the LDl latch is inferred from the technology library. Thus, the procedure implies a certain implementation. This ensures that the required functionality is achieved using the desired libraiy cell. Expanding on this approach, one can develop a library of procedures and functions and easily force the inference of certain technology specific implementations during synthesis. 

G in std jogic signal Q out std jogic signal QN out stdjogic) is -- pragma map Jo cntity LDl 

Design Ware, in addition to its other advantages, provides an effective mechanism to address Scenarios 2 and 3 described in section 10.1. For example, you have several implementations of a module, and wish that the synthesis tool infer the most optimal implementation. This can be achieved using DesignWare libraries. Alternately, if you rattier make the choice yourself than let the tool select an implementation, this can be achieved by placing a dont use attribute on all the undesired implementations or by using the setjmplementation command. 

A synthetic operator is essentially an intermediate stage between reading the HDL source and before a compile step. During the compile step, the inferred synthetic operators are synthesized to one or more technology library cells. To find the different 

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