DesignWare Libraries

Synopsys provides the simulation models for DesignWare components (VHDL models for all components and Verilog models for some), mal g the task of simulation simpler and several times faster. In addition to the components provided in the DesignWare libraries, it is possible to develop and re-use design modules by building a proprietary DesignWare library. 

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Declare the XBLOX designware library (provided by Xilinx) in the syntheticjibrary variable. This allows FPGA Compiler to directly infer the supported XBLOX modules diuing synthesis. 

Identify the location where the intermediate files for the XBLOX designware libraries are stored. 

Use FPGA Compiler to map the design to CLBs and lOBs. The compile command produces a netlist of CLB, lOB, TBUF cells, and a limited number of special cells (latches and adder/subtracter cells from the Xilinx DesignWare library) from the FPGA library. 

Design Ware, in addition to its other advantages, provides an effective mechanism to address Scenarios 2 and 3 described in section 10.1. For example, you have several implementations of a module, and wish that the synthesis tool infer the most optimal implementation. This can be achieved using DesignWare libraries. Alternately, if you rattier make the choice yourself than let the tool select an implementation, this can be achieved by placing a dont use attribute on all the undesired implementations or by using the setjmplementation command. 

Figure 10.1 shows the DesignWare approach to achieving specific implementations. In the HDL code for a procedure similar to the latch proc procedure, if one were to use a map to operator directive instead of a map to cntity directive, the tool would infer the required synthetic operator on reading in the HDL to DC. One must then have a DesignWare library which provides the link between the operator and one or more synthetic modules. Each operator can be linked to multiple synthetic modules and each module can have multiple implementations. Based on the constraints specified, the DC ensures that the most optimal implementation is inferred. 

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