Fabrication techniques lithography

A number of fabrication techniques meet the general requirements for constructing an efficient and compact microreactor. Popular methods include LIGA, wet and dry etching processes, micromachining, lamination, and soft lithography. 

Figure 25.1 Schematics of typical nano and micro fabrication techniques Photolithography, soft lithography, hot embossing, and direct writing. See color plates.

Nanotechnology requires a different approach to fabrication from that of microtechnology. Whereas microscale structures are typically formed by top-down techniques (lithography, deposition, etc.), the practical formation of structures at nanoscale dimensions involves additional components, that is, bottom-up self assembly. 

The processability of certain CEPs has been utilized in the construction of microsystems, particularly miniature sensor systems. For example, simply dip-coating connecting platinum wires with a polyaniline formulation produces a useful humidity sensor.133 CEPs can also be screen-printed or ink-jet-printed to produce the complex shapes needed for various devices. Electrodeposition of CEPs is also a popular processing method, and this technique is compatible with conventional MEMS fabrication, where lithography and etching can be used to prepattern metal electrodes. Subsequent deposition of CEP by electrochemical polymerization produces the CEP microdevice.129... 

Microcontact printing ( J,CP) [17,29,30] is part of a set of nonphotolithographic fabrication techniques known as soft lithography. In iCP, features are patterned with inexpensive, elastomeric PDMS stamps (see Section 5.5.2 for details on stamp fabrication). Consequently, [iCP can be less expensive in terms of capital and operation costs compared to photolithography for patterning large-area micron- or submicron-sized, features [31,32]. 

The French Nuclear Research Center CEA announced the successful fabrication of high performances prototypes fuelled by H2 and based on thin films type structures on Si substrate obtained by micro-electronics fabrication techniques (RIE for fuel micro-channels, PVD for anode collector, CVD, serigraphy, inkjet for Pt catalyst, lithography) with a Nafion membrane [15]. An impressive power density of 300 mW cm with a stabilisation around 150 mW cm" during hundred hours was reported. 

Top-down nanochannel fabrication techniques are developed mainly over the last decade with state-of-the-art micromachining facilities. Various kinds of nanochannels, such as short nanopores, 2D nanoslits, and ID nanotubes, have been fabricated and tested for different applications. Small nanopores are made based on the reflow of surface atoms under the irradiation of focused ion or electron beams. 2D nanoslits can be easily batch fabricated with either etching of enclosed sacrificial lines or bonding of two chips with one having etched nanometer deep open channels on it. ID nanochannels need advanced lithography capability, and many techniques are not suitable for batch fabrication. Some more details of making these three types of nanochannels are as follows. 

Nanochaimel fabrication is an important step to make integrated nanofluidic devices. Solid-state nanochaimel fabrication technique can easily integrate the nanochaimel with other components to make integrated nanofluidic devices because the channel is made with lithography at specified position. However, the cost of solid-state fabrication is usually high, so methods to reduce the cost and to remove the requirement of advanced... 

For example, Collins et al. (2001) proposed a method based on the selective destruction of metallic nanotubes, which could be realized with bursts of electricity. The ropes containing both semiconducting and metallic tubes are deposited on a flat surface of silicon oxide. Then electrodes on the top of the ropes are fabricated by lithography technique. A voltage is applied to the tubes through the electrodes. The metallic CNTs are destroyed by current-induced oxidation, and only the semiconducting tubes remain (carbon nanotubes transistors, http //www.research.ibm.com). However, this technique is only useful for transistor geometries and cannot be extended to bulk separation. 

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