Fabrication and Characterization of Integrated Circuits

With an increase in integration scale it is becoming increasingly necessary to develop tools for the realistic simulation and optimization of the circuitry. An enabling factor is to improve the understanding of device and circuit operation and the awareness of the link between the two. This can be achieved via in-depth transistor modeling, circuit simulation and clever qualitative analysis, as will be discussed after we have introduced our technology. 

Typical transfer and output characteristics of a solution-processed pentacene FET with channel length L = 20 pm and W = 1000 pm are shown in Fig. 13.7. The characteristics were obtained under ambient conditions. The field effect mobility of the FET is 0.01 cm2 V-1 s-1 at Vg = —20 V. On less typical wafers mobilities as high as 0.25 cm2 V-1 s 1 have been observed. The drain current modulation 1d(Vd = —1 V, Vg = -20 V)/ID(VD = —1 V, VG = 10 V) of 10s is routinely obtained. By improving the uniformity and by reducing the parameter spread the integration level could be increased to about 103 transistors. 

In Fig. 13.7 the experimental drain currents are compared with modeled characteristics. Below, the simple nine-term OFET model that is used here will be outlined. Three regimes of operation are distinguished  

Charge transport in the accumulation channel is described by the percolation model [24] based on thermally activated tunneling of holes between localized states in an exponential density of states, described in Section 13.2.2. In the accumulation regime this Variable Range Hopping (VRH) model yields a gate-voltage dependent field-effect mobility of the form  

Using the gradual channel approximation - the lateral electric field does not significantly influence the perpendicular electric field - the drain current in the accumulation regime reads  

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In order to reduce the size of integrated circuits, the technologies used to fabricate them have been continuously changing. As circuit features approach the nanometer scale, it has been proposed that devices (diodes, transistors, resistors, capacitors, and conductive tracks) could be made from molecules with suitable properties, instead of patterned doped silicon layers [65]. For that purpose, it is essential to characterize their electronic properties at the level of single molecules, and the molecular junction methods described above offer many advantages to do it. 

In recent years, the IR absorption of fluorinated silicon oxide (FjcSiOj,) has been actively studied [68-74]. These films are very easily deposited by several PECVD or liquid-phase deposition (LPD) methods and are characterized by a low dielectric constant, which decreases with increased concentration of fluorine in the film. Decreasing the dielectric constant of the intermetal dielectric film is the most efficient way to reduce the adjacent wiring capacitance, which will improve the performance of submicrometer integrated circuits. However, the F SiOy films become reactive to water as the fluorine concentration increases. The film desorbs H2O and HF under thermal annealing after humidification, which causes reliability problems in the VLSI fabrication [68]. 

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