Execution Unit Organization Analysis

Current technology limits the number of global busses to only two or three. Most contemporary commercial microprocessors use two busses. The choice of a two bus scheme has the advantage that dense two-output register cells can be used. This allows busses to be routed directly over functional units and registers in the execution unit because each register can be connected to both busses. The current implementation of SUGAR only understands 2-bus execution units. 

SUGAR determines the number of processing sections in the execution unit based on the following two factors  

For example, the Motorola MC68000 behavior describes a 16-bit memory, 32-bit data registers and 32-bit address registers. Since the instructions are all multiples of 16-bits, the data path should be at least 

16 bits wide. The most frequent effective address computations are 32-bits wide, but the most frequent data computations are only 16-bits. Therefore, SUGAR selects a 16-bit data section and a 32-bit address section. To ensure a good topology, the 32-bit address section is divided into adjacent 16-bit address-low and 16-bit address-high sections. All the sections share the two busses. The busses have bidirectional bus couplers at the section boundaries. This allows the execution unit to be dynamically partitioned into three independent sections enabling up to six parallel bus transfers. 

In contrast to synthesis programs, software compilers normally have a distinct code generation phase since an architecture s rich instruction set often makes it difficult to decide what is the best way to generate machine instructions for an expression. Code generation is usually driven by a library of code selection templates. Each template consists of a pattern tree and a code sequence. The code sequence is emitted when a subtree in the intermediate representation matches the pattern tree. 

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Execution Unit Organization Analysis This phase analyzes the behavior and calculates various parameters such as data width, address width, external data bus width and external address bus width. The relationship between these parameters is used to determine how the execution unit should be organized. Execution unit organization analysis is described in Section 7.3. In contrast, EMUCS does not perform a similar analysis. This task is necessarily specific to the microprocessor because in the general case, separate address and data sections cannot be assumed. 

Expression Context Analysis This phase analyzes each expression in the behavior and determines how it is used in relation to the expressions surrounding it. For instance, the result of an expression may be used only as a memory address. This information is recorded and used later by a synthesis phase to assign an appropriate type of register to the expression. As for Execution Unit Organization Analysis, this phase is specific to microprocessor design. 

Code Generation Code generation maps the expressions and procedures at the behavioral level to a list of uncompacted control sequences and a network of symbolic units using a rule base to select alternative ways to synthesize each behavioral expression. Symbolic busses are also generated in this phase. The rule base is selected based on the information recorded by the execution unit organization analysis phase. Code generation is described in detail in Section 7.4. 

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