Ethernet co-processor

The Ethernet co-processor [GC91] manages Uansmitting and receiving data frames over a netwoilc under CSMA/CD protocol. CSMA/CD refers to the Carrier Sense Multiple Access with Collision Detection protocol [TanSl], a protocol which is used to facilitate communication among many stations over a shared channel. Any station wishing to transmit listens first to the line and defers its transmission until the channel is clear. Multiple stations are allowed to simultaneously access the channel without use of any central arbitration. The protocol is defined by the IEEE 802.3 standard. 

The host CPU invokes the Ethernet co-processor by writing to a memory mapped address. The co-processor responds by making a request for control of the address/data bus. When bus control is granted, the co-processor initiates a memory read operation to receive command operations and then releases control of the bus. The co-processor provides a small execution unit with four instructions that let the host processor program the co-processor for specific operations, e.g. transmit some data from memory. The unit also gives the co-processor 

The co-processor contains two independent 16-byte wide receive and transmit FIFO queues. Direct memory access (DMA) is supported to off-load the processor during reception and transmission. To receive data frames from the Ethernet line, the host CPU reserves a buffer space in main memory and invokes the co-processor. The asynchronously arriving data frames are received by the co-processor and stored into a local memory. A DMA receiver module then writes the data frames to main memory. To transmit data on the Ethernet line, the host CPU invokes the co-processor with a pointer to the location in main memory containing the data. The co-processor consmicts a data frame by reading the data fields from main memory and then transmits it over the Ethernet 

Block controller is the top-level model containing an interconnection of processes. Process execjunit is the execution unit that controls the transmission and reception of data frames. Processes DMAjrcvd and DMAjcmit are responsible for communicating with the main memory through the shared bus. Processes recv rame and xmit/rame are responsible for receiving and sending data frames on the Ethernet line. These two processes are central to the co-processor. 

The extensive use of external synchronization in the design implies that the length of the schedule cannot be statically defined. We therefore estimate the scheduling cost by two measures A which represents the total number of anchors in the SIF model, and which represents the sum of the 

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Detailed timing constraints. These constraints specify strict timing relationships, represented as minimum and maximum bounds on the activation of operations, that affect the externally visible behavior of a given module. For example, we may require the Ethernet co-processor to read the address/data bus at most 8 cycles after the rising edge of a request signal, and consecutive writes to a bus should take place at most once every 2 cycles. 

Table 11.1 HardwareC description statistics for the Ethernet co-processor.

Synthesis results. The final design was mapped to an implementation in LSI Logic s LCAIOK Compacted Array library with a cycle time of 67 nanoseconds to sustain a IS MHz clock frequency. Implementation statistics include the number of registers, the area cost using library parameters, and the critical path delay in nanoseconds. As in the Ethernet co-processor design, we estimate the scheduling cost as the sum of the maximum offsets in the relative... 

Most synthesized designs require complex coordination with their environment to meet handshaking and timing protocols. For example, the Ethernet co-processor design demonstrates the extensive use of external synchronization in both specification and synthesis. The underlying hardware model for both HardwareC and Hebe allows these communication requirements to be clearly specified and enforced in the synthesized hardware. 

To receive data from the Ethernet line, the host CPU sets aside an adequate amount of buffer space and invokes the co-processor by writing to a memory mapped address. The co-processor responds by requesting bus control, and then reading the command instruction from memory. Upon enabling the coprocessor in receive mode, the asynchronously arriving data frames are stored into a free memory area. Once an entire error-free frame is received, the coprocessor fetches the adress of the next free receive buffer and interrupts the CPU. Transmission of data is performed in a similar manner. 

Even with the implementation of gesture control, the control data of the display must be transferred from an external controller to the MB88F334. After the co-ordinates have been processed internally, they can be transferred to the host processor via the Media Independent Interface (MET). The Mil interface enables the use of the APIX2 link as an Ethernet bit transmission layer (PHY) and provides fuU duplex operation up to 100 Mbit/s. The sideband link therefore represents the link between the host processor, sensors and the display. 

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