DesignWare

You have read in your design. DC shows inferred DesignWare parts named, DW . How does one ungroup the DesignWare part inferred Even after compiling the design, the DesignWare parts exist as separate levels of hierarchy. 

You are creating your own designware modules. Is there a way to attach an attribute to all my Design Ware components so that one can easily find them after compile. 

The following message will be issued during compile indicating that this attribute has been added to your DesignWare component... 

Declare the XBLOX designware library (provided by Xilinx) in the syntheticjibrary variable. This allows FPGA Compiler to directly infer the supported XBLOX modules diuing synthesis. 

Identify the location where the intermediate files for the XBLOX designware libraries are stored. 

Use FPGA Compiler to map the design to CLBs and lOBs. The compile command produces a netlist of CLB, lOB, TBUF cells, and a limited number of special cells (latches and adder/subtracter cells from the Xilinx DesignWare library) from the FPGA library. 

Synopsys provides the simulation models for DesignWare components (VHDL models for all components and Verilog models for some), mal g the task of simulation simpler and several times faster. In addition to the components provided in the DesignWare libraries, it is possible to develop and re-use design modules by building a proprietary DesignWare library. 

In this section, we discuss certain common scenarios with regard to inferring complex cells. This helps one to understand the DesignWare mechanism and how it can be used to infer complex cells which are difficult to infer via synthesis. 

For each of the scenarios discussed above, DesignWare provides an effective solution as described in section 10.3. 

Example 10.1 shows the mechanism by which the predefined arithmetic operation, in VHDL is mapped to DesignWare components. The operation in the VHDL code for data type unsigned operands is mapped to the corresponding function in the std Jogic arith package. This function in turn calls the function mult which is mapped to the DesignWare synthetic operator MULT UNS OP. 

Example 10.1 Arithmetic Operation Mapped to DesignWare Component... 

Design Ware, in addition to its other advantages, provides an effective mechanism to address Scenarios 2 and 3 described in section 10.1. For example, you have several implementations of a module, and wish that the synthesis tool infer the most optimal implementation. This can be achieved using DesignWare libraries. Alternately, if you rattier make the choice yourself than let the tool select an implementation, this can be achieved by placing a dont use attribute on all the undesired implementations or by using the setjmplementation command. 

Figure 10.1 shows the DesignWare approach to achieving specific implementations. In the HDL code for a procedure similar to the latch proc procedure, if one were to use a map to operator directive instead of a map to cntity directive, the tool would infer the required synthetic operator on reading in the HDL to DC. One must then have a DesignWare library which provides the link between the operator and one or more synthetic modules. Each operator can be linked to multiple synthetic modules and each module can have multiple implementations. Based on the constraints specified, the DC ensures that the most optimal implementation is inferred. 

You may either allow DC to evaluate and select the best implementation or use the setjmplcmcntation command to select your implementation. Further, there are attributes available in Designware like priority and legality which allow you to specify the priority among different available implementations (rather than pennitting DC to evaluate them) and the parameters for which that implementation is a legal (allowed). 

You have instantiated the DesignWare component DW03 updn ctr in your code. On compile, DC gives the following error ... 

You want to add two 8-bit numbers A and B using a 8-bit DesignWare adder such that carry out bit of the DesignWare adder is used to give a 9 -bit result. 

You are creating a DesignWare libraiy and licensing out the parts to other customers. You want to encrypt the VHDLA/erilog models and then send them out to the customers. Is this possible ... 

You wish to attach an attribute to a Designware component. How do you go about doing this ... 

You are using Designware Developer to create a synthetic operator "EQ UNS OP" synthetic module and implementations of the operation. How can one automatically infer this Designware component for the operation in the Verilog code. 

The "==" operation in Verilog is not mapped to a DesignWare component. One way to map the " operation to your Designware component is by using the "map to operator" pragma in a function call as shown in the example below ... 

---