Mapping to DesignWare Components

Example 10.1 shows the mechanism by which the predefined arithmetic operation, in VHDL is mapped to DesignWare components. The operation in the VHDL code for data type unsigned operands is mapped to the corresponding function in the std Jogic arith package. This function in turn calls the function mult which is mapped to the DesignWare synthetic operator MULT UNS OP. 

Example 10.1 Arithmetic Operation Mapped to DesignWare Component 

The code in Example 10.2 can be read into DC and synthesized without any errors, though the operation will be built using random logic. This is because, for scalar data types, the predefined relational operators are implicitly defined. 

Example 10.2 Arithmetic Operation Built from Random Logic 

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The "==" operation in Verilog is not mapped to a DesignWare component. One way to map the " operation to your Designware component is by using the "map to operator" pragma in a function call as shown in the example below ... 

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