Damaged surface layer semiconductors

Further experimentation will be required to obtain more direct evidence of high dislocation densities and to show quantitative correlation with electrical and other properties. If such evidence cannot be found then another explanation must be sought to account for the properties of damaged surface layers on semiconductors. 

Electrolytic etching of semiconductors is used to remove damaged surface layers on single crystal material and/or shape... 

It should be noted that dielectric and optical properties of the near-the-surface layer of a semiconductor, which vary in a certain manner under the action of electric field, depend also on the physicochemical conditions of the experiment and on the prehistory of the semiconductor sample. For example, Gavrilenko et al (1976) and Bondarenko et al. (1975) observed a strong effect of such surface treatment as ion bombardment and mechanical polishing on electroreflection spectra. The damaged layer, which arises in the electrode due to such treatments, has quite different electrooptic characteristics in comparison with the same semiconductor of a perfect crystalline structure (see also Tyagai and Snitko, 1980). 

If the surface of a single crystal n-type semiconductor is damaged by abrasion or by high energy particle bombardment, the generation (recombination) velocity for holes in the surface layer is increased to the extent that holes are readily available to carry out anodic reactions at a rapid rate. This condition lasts until most of the damaged surface material is removed. Then the anode current is limited as previously described due to hole depletion. 

In the top-gate architecture, the semiconductor is deposited before the gate dielectric and the gate electrode. This has several advantages. First, since the semiconductor is deposited on a known surface (the substrate itself, in typical examples), it is possible to exploit the fact that this substrate is typically extremely smooth and of known chemistry to ensure that the quality of the printed semiconductor is maximized. Most current in a transistor flows very close to the semiconductor-dielectric interface. In a top-gated transistor, therefore, this current flows near the top interface of the semiconductor this may then be optimized to maximize the quality of the same. Additionally, since this layer is covered by the dielectric and gate, it may be protected from damage from subsequent process steps, etc. 

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