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Wafer-level CSP

Silicon die wire-bonded to polyimide tape Wafer-level CSP (WLCSP)... [Pg.253]

Thin-film redistribution process using wafer-level passivation and cyclotene dielectric High-performance wafer-level CSP, JEDEC MSL 1 UltraCSP (Flip Chip Technology, Amkor and K S Flip Chip Division of Kulicke Sofia) EEPROM, Flash memory, DRAM, and standard electronic devices, PDAs, laptop PCs, disk drives, GPS, and MP3 players... [Pg.319]

Other component reliability issues related to lead-free solders include flip chips and wafer level CSPs with lead-free solder bumps and balls, where the higher soldering temperature and higher stiffness of the lead-free solder can adversely effect the reliability of the low-k dielectric layer on the die. Low k dielectric is needed for high speed applications, but is typically more fragile and prone to cracking. [Pg.14]

See other pages where Wafer-level CSP is mentioned: [Pg.18]    [Pg.19]    [Pg.319]    [Pg.20]    [Pg.321]    [Pg.77]    [Pg.94]    [Pg.107]    [Pg.110]    [Pg.18]    [Pg.19]    [Pg.319]    [Pg.20]    [Pg.321]    [Pg.77]    [Pg.94]    [Pg.107]    [Pg.110]    [Pg.435]    [Pg.18]   
See also in sourсe #XX -- [ Pg.18 , Pg.253 ]



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CSPs

Wafer-level CSPs

Wafers

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