Via-in-pad design

Improving the stability of solder paste printing volnme for via-in-pad designs... 

Conductive Paste. In addition to the previous advantages of via filhng stated earlier, conductive via fills also dissipate heat, increase electrical conductivity in the hole, and allow a via-in-pad design option (Fig. 22.17). The latter advantage is another way to recover real estate. 

FIGURE 22.17 A via-in-pad option with conductive via fill (a) traditional dog-bone design (b) via-in-pad design. (Courtesy of DuPont)... 

Smaller holes and increasing circuit density are drivers that pnsh technology for via-in-pad and stacked microvia designs that help minimize PWB real estate. It has been established that via-in-pad designs, where the via is not filled, can lead to voids in the BGA solder joint that can negatively affect reUabUity. 

Platability—Cu Adhesion. More frequently, designers are specifying that the material used to plug the hole be platable so the real estate can be reclaimed as in via-in-pad designs or in subcomposite structures. Such applications require a material that can be roughened, catalyzed, and plated with good copper adhesion. 

PCB Enhancement Solder filled via (HASL) Plated or filled vias Offset via-in-pad design / offset print... 

Designs with via in pad may preclude meeting diese criteria. Solder acceptance mteria should be defined by the user and the manufacturer. These criteria are for chip components diat may flip (rotate) onto the narrow edge during assembly. 

Figure 18. The void is formed by air entrapped during the print process as occurred in a cross section of dry solder paste (Figure 19). Experimentation has demonstrated a reduction in the occurrence of via-in-pad voids through PCB design or printing process modifications. Several options for void reduction are listed in Table 10.

Devices used in circuits have one major difference with test devices- there are usually many fewer bond pads in the design, and therefore less opportunity for gate leakage into the device because of vias to the gate layer. The same guidelines apply, and a forbidden zone at least a wide should be respected around vias. 

Table 9.4 lists several of the key variables that influence an overall via-to-innerlayer pad registration capability in the printed circuit manufacturing process. The values in the table represent individual process standard deviations using a specific multilayer circuit design. If we make the assumption that these processes are normally distributed and that they are centered on the desired nominal value, we can use additivity of variance to estimate an overall registration capability. In other words, taking the square root of the sum of the squares of each individual process standard deviation gives an overall process standard deviation that can be used to assess capability. 

Shape-based Router. This type of router recognizes shapes already placed in a wiring surface and routes wires to avoid them. Spacing between wires and other objects, such as vias, used to change layers and component pads is maintained as the router places a wire in a space. This router is becoming the workhorse of SMT-based designs. 

As design features are continually reduced to produce higher-density interconnects, tighter control of every step in the conductor formation process is required to achieve high yield. The maximum possible yield with an etching or plating process depends on the conductor dimensions such as the conductor pitch in terms of line and space, the conductor thickness, and the size and shape of the capture pads around plated through-holes (PTH) and vias. 

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