Uniprocessor computers

Unipol PP process Unipol process Uniprocessor computers UNIQUAC UNISITALE process... 

The DESP ensures the physical input and output. In the Mediterranean LGV application, the DESP was implemented in an input/output basket with a coded uniprocessor computer, a CKD and ouQ)ut cards (CSS cartes de sorties), and safety input cards (CES cartes d entree de securite). In recent applications (Spain LGV), the DESP is implemented using MTOR cards (processor card with encoded COLDFIRE and CKD integration), handling 48 inputs/outputs on a single card. 

The redundant computer DIGISAFE XME is based on a redundancy management protocol that allows two coded uniprocessor computers to work as symmetrically as possible. Each computer (called units) is intrinsically safe, and the maintenance of consistency between the execution contexts of the two units allows the switching or transition to the non-redundant (isolated) unit at any time, without requiring special precautions at the application or system level. This last point is extremely important because it significantly reduces system complexity and the associated safety analysis. 

A recent victim of the killer micros was Evans and Sutherland s parallel computer development effort, halted ia 1990. Their architecture combiaed a small number of approximately 1-MFLOPS processors iato semi-iadependent functional units. Several of these units could, ia turn, be combiaed to form a processor hierarchy, building up to systems that were expected to cost between 1 and 8 million dollars. With the advent of lO-MFLOPS uniprocessor killer micros, such an architecture became irrelevant and the project was halted. The RISC killer micro could deUver the same level of performance as could the combiaed efforts of 10 of the 1-MFLOPS processors, evea with the unlikely assumptioa that the problem could be perfectiy parallelized across 10 processors. 

NUMA is one of the fundamental concepts needed to understand the design of a parallel software application. Every modern computer has several levels of memory, and parallel computers tend to have more levels than uniprocessors. Typical memory levels in a parallel computer include the processor registers, local cache memory, local main memory, and remote memory. If the parallel computer supports virtual memory, local and remote disk are added to this hierarchy. These levels vary in size, speed, and method of access. In this chapter, we will lump all these differences under the general term nonuniform memory access (NUMA). Note that this is a broader use of the term than is often found in computer science literature, where NUMA often refers only to differences in the speed with which given memory items can be accessed using the same method. In our use, memory access is often synonymous with data transfer. ... 

The processing node of a cluster incorporates all of the facilities and functionality necessary to perform a complete computation. Nodes are most often structured either as uniprocessor systems or as SMPs although some clusters, especially constellations, have incorporated nodes that were distributed shared memory (DSM) systems. Nodes are distinguished by the architecture of... 

Most modem minicomputers have multiple processors with a single address space that, as such, are termed multiprocessors. The processor count present in a purchased computer is based on the user needs, usually with the capability to add additional processors as use requirements increase. These processors are typically the same ones that are used in personal and mainframe computers. It is generally agreed that the multiprocessor composed of several uniprocessors provides a better cost/performance ratio than building a comparable uniprocessor using enhanced technology. 

For ground equipment TVM 430, and to meet the above constraints, the coded uniprocessor technology was modified and the ground safety computer TVM 430 divided into four blocks supported by four electronic cards. 

Currently over 1,000 ONBOARD TVM 430 devices are in operation. These devices use coded uniprocessor technology. The ONBOARD TVM 430 computer... 

This chapter presented the original architecture of the coded uniprocessor technology and dual processor architectures. The evolution towards a two of three-type computer (2oo3) was made in order to ensure the storage of safety information and hot recovery after a breakdown (application context recovery). 

---