Stanfords Olympus System

HardwareC, a version of C extended to support processes, interprocess communication, memory modules, parameter classes (in, out, inout), architectural registers, combinational operations, and Boolean and integer variable tjrpes. 

HardwareC also supports timing constraints and resource constraints. 

Uses a sequencing graph model, called the Sequencing Intermediate orm (SIF), for scheduling and allocation. The vertices of the graph represent operations to be performed, and the edges represent predecessor / successor relationships (which are subject to the data dependencies between operations). 

Vertices may either be state vertices, requiring at least one cycle for execution, or stateless, requiring no time to execute. 

User-driven transformations allow the user to expand procedure calls inline, or to specify the library modules ibat should be used to implement particular operations. 

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Hercules and Hebe are part of the Olympus Synthesis System. For availability information, please send electronic mail to olympus chronos.stanford.edu. 

The high-level synthesis research described in this book is part of an on-going synthesis research project at Stanford University called the Olympus synthesis system. We would like to acknowledge and thank the many people who have contributed to this research. 

In addition, we developed a hardware description language called Hard-wareC with particular attention to ASIC design specification issues. The system implementation of the algtaithms is provided by programs Hercules and Hebe, which serve as the front-end to Stanford s Olympus Synthesis system. They have been applied to the synthesis of benchmaric examples and to some chip designs at Stanford University. 

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