Serialized Channel in the 3rd Dimension

If the 2.5-D technology is available, it s possible to re-organize the RDRAM chip so that the signal path can be significantly reduced. Suppose we need to design a memory system composed of four RDRAM chips. In the conventional solution, the four chips will be serially connected as shown in Fig. 3.5. In a 2.5-D stacked memory system illustrated in Fig. 3.6, the DRAM cells can now be placed into four layers and vertically stacked. The memory bus will be through inter-chip contacts, which have only a vertical height of 50 pm. As a result, 2.5-D stacked Rambus DRAM has a considerable potential to achieve superior performance at a relatively low cost. 

Moreover, since the stacked RDRAM is a complete system, it can be built with larger freedom. For instance, a 2.5-D RDRAM can be configured as one single RDRAM channel or multiple channels by properly grouping internal banks in the vertical direction. One such a 4-channel configuration is shown in Fig. 3.6. Here one channel consists of 16 banks placed into four layers with data flowing as the indicated by the arrows. 

From the above analysis, one can see that the 2.5-D integration style can greatly help build faster DRAM memories in two aspects (1) allow more efficient layout organization, and (2) removing inter-chip bus connecting. 

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