Polysilicon CMP for Deep Trench Capacitor Fabrication

Each cell in a DRAM circuit consists of a transistor and a capacitor. In the operation of a DRAM, information is stored in each memory cell as either the presence or absence of charge on the capacitor. As with most ICs advancements in DRAM memory density and cost are made by scaling the dimensions. However, as capacitor dimensions are scaled, the amount of charge that may be placed on the capacitor is reduced. In order to maintain the integrity of the stored data, it is necessary to mountain the amount of charge that may be stored on the capacitor and hence maintain the capacitance through each successive generation of smaller circuits. 

RE etch back or CMP may be used to remove the polysilicon overburden. When RE etch back is used, however, a center seam is etched into the trench. In addition, the RE etch is not self-arresting, and therefore leads to a step at the oxide-polysilicon edge. These defects reduce planarity and make it difficult to reliably cover the trench with the strap film. Center seam and edge step defects in deep trench formation are analogous to the same defects that form when RE etch back is used to remove the 

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