Pattern Density Dependency

Choi J, Dornfeld DA. Modeling of pattern density dependent pressure nonuniformity at a die scale for ILD chemical mechanical planarization. Mater Res Soc Symp Proc 2004 816 K4.4.1-K4.4.6. 

FIGURE 12.9 AFM post-CMP measurements illustrating pattern density dependence of polish rates for different patterns on the same wafer (a) different feature size, same spacing and (b) different spacing, same feature size. 

Note that pattern density dependence in the metal polish rate does not occur at contact and via levels. ContactAia fill requires conformal metal deposition which, because of the small dimensions of the contact/via, results in planar surfaces, as shown in Figure 7.38a. Here, the pressure is uniform across the surface during metal removal, and a pattern dependency to polish rate only occurs during the overpolish step. In contrast wider structures seen at the interconnection level are not planar after metal deposition... 

Characterization of pattern density dependency are conducted on 4 mask sets with different device blocks and pattern densities ... 

Pattern density dependency, arising for system-on-a-chip design, is characterized with CMP process optimization, slurry selectivity, over-polish extent and dummy pattern structure. For low density devices, dummy structure is desirable under conditions that the supportive dense structure could exceed a threshold value for reduction of CMP erosioa Physical and electrical evaluations help to identify the process window for different density structure. The characterized SIT process feature will allow designers to print circuit patterns more efficiently and cram more fiinctions onto the silicon. 

Figure 7 Normalized nitride thickness at different density features for wafers without dummy structure. The pattern density dependency is very sensitive to over-polish sequence. 

The model by Grillaert et al. addresses step height dependencies and includes a density dependence. Smith et al. [48] integrated the effective pattern density model described earlier with the time and step-height dependent model of Grillaert et al. to accurately predict both up and down area polishing. The resulting analytic expression for the up area amount removed (AR) is... 

A key benefit of accurate CMP models that needs emphasis is the capability to optimize layout design before polishing. Post-CMP ILD thickness variation is a serious concern from both functionality and reliability concerns. An effective method of minimizing this effect is the use of dummy fill patterns that lead to a more equitable pattern density distribution across the chip. Evaluation of such schemes before actual product implementation has become a major use of CMP modeling [53]. Dummy fill is also being investigated for front-end processes where shallow trench isolation CMP suffers from substantial pattern dependencies. 

When dishing occurs in a patterned wafer, the ILD beside the dished area polishes faster than the ILD in isolated field regions. The ILD height difference between patterned and field areas, shown in Fig. 5.20, is called erosion. Experimentally, erosion depends on the pattern density. 

Equation 5.10 predicts an exponential decay to the final dishing depths, with the decay rate dependent on various parameters described above. This expression for dishing as a function of time, linewidth, and pattern density is compared to experimental data in Fig. 5.21. 

CMP was first developed at IBM East Fishkill in 1983 and is being used for copper planarization since the late 1990s. An important characteristic of CMP is that it planarizes Cu across the wafer with least dependence on pattern densities compared to other methods. An inadequate planarization will lead to... 

The copper-clearing step is a conventional planarization process. This step introduces most of the topography on the wafer. The two main reasons are the dependency of the copper removal rate on the wafer pattern density and the fact... 

Erosion <50nm >100nm Relaxed Depending on pattern density... 

Erosion Dielectric erosion depends on pattern density and has to be kept below 50nm in microelectronic array structures [14]. Erosion can also occur in microfabrication when pattern arrays have to be planarized. Due to larger vertical and lateral dimensions, the requirements are relaxed compared to microelectronics. 

Copper dishing vs. linewidth for several pattern densities. Dishing is a strong function of linewidth, but only weakly dependent upon pattern density. 

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