Master logic diagram

Fig. 6.3-3 Core Damage Master Logic Diagrams for Indian Point 2 and 3 Nuclear Power Stations.

Hazard Identification, the main sources of ammonia that could release are identified and the initiating events (IE) that can cause accidents leading to the release of ammonia are determined. Three methods used for IE identification were Master Logic Diagram, checklists, and HAZOP... 

Use of analytical methods such as hazard and operabiUty analysis (HAZOP), failure mode, effect analysis (FMEA) , and master logic diagrams ... 

The methods used to identify PIEs should be described. This may include, among other things, the use of analytical methods such as master logic diagrams, hazard and operability analysis, and failure mode and effects analysis (FMEA). Initiating events that can occur owing to human error should also be considered in the identification of PIEs. Whichever method is used, it should be demonstrated that the identification of PIEs has been performed in a systematic way and has led to the development of a comprehensive list of events. 

An outgrowth of the master logic diagram to represent all the physical interrelationships among various plant systems and subsystems in a simple logic diagram. It is used for probabilistic assessments to model and Integrate the relationship between all plant functions and equipment (Mauri, 2000). 

Qualitative reliability analysis are used to identify possible ways in which a system can fail. The calculation can result in all combinations of components and human failures that lead to safety (protection) system failure, which prevents the safety system to shut-down the reactor upon request. For this analysis a top-down logic model, known as a Master Logic Diagram (MLD), similar to a fault-tree, could advantageously be used with a top event of a safety system failure upon request. The results of this analysis can be used to prove the fulfillment of the important single failure design criteria. 

Extended master plan logic diagram (MPLD)... 

Set-Reset Latch Truth Table Set-Reset Latch Macrotiming Diagram J K Latch T Latch D Latch Synchronous Latches Master-Slave Flip-Flops Standard Master-Slave Data Flip-Flop Sequential Logic System Description... 

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