Set-reset latch

A latching circuit waits for an event to occur. Once that event occurs, the latch output changes state and will ignore any further events until reset. This can be described as a memory element. The latch has many applications in the system. For example, if a failure mode occurs in the system, a shutdown signal may be sent to the latch circuit, which will shut down the system and prevent any further possible damage. The system will remain shut down until the power to the system is recycled. 

The power to the latch is not shown in the schematic. A +5-V DC input was used to power the digital ICs. 

The truth table for the set reset latch is shown in Table 5.2. 

In order to show the performance of the set-reset flip-flop, a series of events were initiated. The reset pin of the flip-flop was first set high, then low. This allows the flip-flop to read and react to a change-of-state event on the set pin. A pulse was then applied to the set pin. When the set pin transitioned from low to high, the output (Q) of the 

TABLE 7.2 Truth Table for Set-Reset Flip-Flop 

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The photochromism of (109) was applied to the straightforward small-scale integration of seemingly complex set-reset latches.The complex of (109) with CdSe-ZnS core-shell acted as a quantum dot. ... 

Combinational and Sequential Logic Circuits Set-Reset Latch... 

Latch Analysis with Difference Equations Microtiming Diagram Construction Set-Reset Latch Nomenclature... 

Set-Reset Latch Truth Table Set-Reset Latch Macrotiming Diagram J K Latch T Latch D Latch Synchronous Latches Master-Slave Flip-Flops Standard Master-Slave Data Flip-Flop Sequential Logic System Description... 

TABLE 1.22 Output Status of Set-Reset Latch with Low Inputs... 

TABLE 1.24 Effect of a High Input on a Stable Set-Reset Latch signal... 

FIGURE 1.59 Microtiming diagram example for the set reset latch (a) specified driving and initial conditions, (b) output-2 advanced to t2, (c) output-1 advanced to t2, (d) outputs advanced to fio. 

TABLE 1.25 Asynchronous Set-Reset Latch Truth Table... 

A semiconductor electronic analog of the above is the R-S flip-flop (or set-reset latch), prepared from two cross-wired and fed-back NOR gates (Figure 2), where the states of the inputs R (reset) and S (set) allow a memory to be held and read along the output lines A and B, according to the truth table (Table 2). 

A set-reset (SR) latch in a stable state is changed to a different stable state by a high external input to the gate, which has the initially high output. The new state remains stable with the new value and continues to remain stable when the external input is removed. If the external input to a gate is less than the other gate s output there is no change in state. This output status is charted in Table 1.24. 

FIGURE 1.60 The set-reset (SR) latch (a) circuit diagram, (b) SBS representation. 

Figure 12. Logic circuitry generated by Janus to implement an interface adapter between the Multibus (see Figure 4) and a microprocessor (see Figure 11). The logic only implements the master read operation. Note the set of latches on the upper right used to capture events. The latch at the bottom enables the output latches when the operation starts and resets them when the operation ends. Further details on this and other examples can be found in [81. ...

Figure 6.80 This is an alternative latching scheme with three stages hold, reset and set. First the clock is at the hold state, then it comes down to its reset voltage. In the set state, it takes relatively little current to set the latch to a high state. Once the latch is set, the clock moves to the read or hold state.

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