JK flip flop

Using JK flip-flops, we can design a circuit that will count a clock signal and provide a divided output of that clock signal. 

The resulting breadboard waveforms are shown in Fig. 7.2. The top waveform is the 100 kHz clock, the middle waveform is the Q output of the first JK flip-flop stage (divide by 2), and the bottom waveform is the Q output of the second JK flip-flop stage (divide by 4). This circuit was simulated using IsSpice, PSpice, and Micro-Cap. The results of each of these simulators are shown in Figs. 7.3, 7.4, and 7.5, respectively. 

The schematic of the staircase generator circuit is shown in Fig. 7.18. Not shown in the schematic is the power to the JK flip-flops and the AND gate. A +5-V DC input was used to power the digital ICs. 

UA723 for the op-amp, CD4027 for the JK flip-flops, and a CD4081 for the AND gate. 

The breadboard staggered Q outputs of the first four JK flip-flops are shown in Fig. 7.19. Figures 7.20, 7.21, and 7.22 show the results of the IsSpice, Micro-Cap, and PSpice simulators, respectively. 

Normally, one would not have to connect a clocked flip-flop into the JK mode since many integrated-circuit JK flip-flops are available (see Fig. 23.15). Notice that the gated S and C inputs are renamed J and K. The connections from J and K to Q and Q are made internally and usually do not appear on the diagram. 

In addition to the RS, clocked, and JK flip-flops, there are others developed for many varied applications of input gating, including capacitor coupling for AC-only operation. 

A data latch can be built using JK flip-flops, clocked flip-flops, and all varieties of synchronous master-slave flip-flops (see Figure 23.17B). The clocked flip-flop data-latch operates in much the same way as the RS flip-flop data-latch the TP line must undergo a negative-going 1 to 0 transition each time data is transferred. However, the clocked flip-flop data-latch will operate only in a synchronous manner (that is, each time a negative-going clock pulse is present), in contrast to the RS flip-flop data-latch, in which the outputs will follow the inputs whenever the TP input is 0. 

The simplest shift-register is the serial I/O type, shown in Figure 23.18 (omitting the dashed-line outputs). The 4-bit register presented is constructed from master-slave clocked flip-flops. (It can also be constructed from JK flip-flops in exactly the same manner but it cannot be constructed from RS flip-flops.) Notice that a shorthand notation, with the AND gate symbols omitted, is used for the clocked flip-flops. 

Often one needs counters in an interface to divide down the clock frequencies and to count such events as the number of data points taken and the number of times data exceed a predetermined threshold. The flip-flop used in modern integrated-circuit counters is the master-slave JK flip-flop. It is used to construct two basic types of counters, asynchronous and synchronous, that will count up or down in a variety of counting schemes. 

Design a divide-by-25 circuit using JK flip-flops. 

This occurs because the S3mthesizer does not see a JK flip flop in the process function but knows, from the clock condition in the Wait statement, that a sequential circuit is being inferred. As discussed in section 5.1.3, the choice of flip flop in an inferred sequential section is left entirely up to the synthesizer. It will therefore tend to select a simple one rather than a complex one, and so not risk the overspedfication of the circuit. Observe the feedback of S, which is required to determine the next state of the circuit. Because this signal is not only updated and output by the process but also read, the connection to the top level of the drcuit is defined in the schematic as bidirectional. This does not mean that it can be used as an input to the circuit as the entity declaration for this component states that the port Q, to which it is directly connected, is of mode output. 

The statistics for these two circuits are shown in Table 5.3. As expected, they indicate that the drcuit for the JK flip flop is three times as large as the one for the D-type. The delay figures given in this table compare the effects of the front-end combinational logic on each circuit. They indicate that the longest delay for an input signal to reach the latch in the JK flip flop is well over double that of the D-type. 

The optimized JK flip flop has had this same logic removed, but also much more. In fact, as Figure 5.24 illustrates, it is almost beginning to re-... 

The optimization statistics in Table 5.3 show that the JK flip flop has had almost two-thirds of its logic stripped out whereas the transistor coimt for the D-type has only fallen by one-fifth. This demonstrates the highly circuit-dependent nature of the optimizer s success and that an efficient VHDL description does not guarantee that the synthesizer will produce a good circuit. 

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