Interface Timing Constraints

This chapter describes CSTEP, a scheduling algorithm that uses techniques drawn from microcode compaction. Unlike other approaches, CSTEP has a primary goal of dealing with interface timing constraints as well as performance and area constraints. 

In contrast, interface timing constraints are concerned with the relative timing of a small set of individual signaling operators. Interface protocols specify minimum and maximum values for these operations but do not specify the timing of unrelated operators. For this reason, interface timing constraints are best expressed on individual pairs of operators rather than intervals containing several operators. 

CSTEP supports interface timing constraints which specify minimum and maximum times between operations. Constraint declarations in CSTEP describe a constraint name, a time interval between operators, and an inequality with a constant that is expressed in either nanoseconds or clock periods. For example, the following maximum-time constraint specifies that operator xl must execute at least 80ns before operator x2 ... 

This chapter has described the design and implementation of CSTEP, the Workbench scheduling tool. CSTEP was designed for speed and flexibility and supports scheduling with resource constraints and interface timing constraints. 

The need to represent and synthesize circuits with interface timing constraints has led to the development of event graphs as described in the previous section. The nodes of these gr hs correspond to signaling events and the arcs specify how the events are ordered and separated in time. This model freely mixes synchronous and asynchronous interface behavior. However, only limited data-flow information is captured, namely, when input and ouQ)ut data values must be valid on the interface signal wires. 

Data arcs connect the interface behavior to the internal behavior. A data dependency arc from an input event to an operation signifies where and when the input data Hornes available on the interface. A data arc from an operation to an output event signifies where and when output data is to be presented on the interface. Timing constraint arcs are propagated to the data-flow from the interface specification. 

Poor operator interface design induces errors and inefficiency among even the best-trained operators, especially under conditions of stress, time constraints, and/or fatigue. Although labeling (e.g., user documentation) is extremely important for good performance, even well-written instructions are cumbersome to use in conjunction with actual operation. In addition, it is difficult to write coherent documentation that describes awkward operating procedures. 

Derived requirements needed for hardware/SAV integration, such as definition of protocols, timing constraints, and addressing schemes for the interface between hardware and SAV. 

INPUTP and OUTPUTP operators specify when values are read from and written to the external ports of the bus interface. OUTPUTP operators can be used with symbolic constants to enable and disable tristate output ports. The timing constraints in the specification are expressed on operators by adding labels using ISPS qualifiers and referring to these labels in the timing constraint specification. 

The HMI (human machine interface) encompasses displays, alarms and manual controls. Evidence shows that human reliability is not good in high-pressure situations with serious time constraints. For this reason, normally only weak reliability claims (typically of the order of lO pfd) are made for operators in fault situations, and it is normally assumed they do not have to react quickly. Consequently there is little purpose in designing an extremely high reliability HMI, so it is normally just a SIL 1 system. 

An optimum chamber pressure for turkey meat has been found experimentally by Sandall et al. [62] and has also been established through theoretical analysis [12]. Litchfield et al. [61] compared cyclic pressure and near-optimal constant pressure freeze drying processes in a situation in which operation at a pressure that would minimize drying time was not possible because of an interface temperature constraint at no time during the entire run did the cycled pressure process prove superior. In view of these considerations, it may be inferred that for materials exhibiting an attainable optimum with respect to pressure, there will be no advantage in cycling the chamber pressure when compared with near-optimal constant pressure operation. 

There are two important features to this synthesis method. First, the circuit is composed piecemeal using relatively simple algorithms and then combined into a single circuit that properly orchestrates the interactions among the parts. Second, the fastest possible circuit is synthesized rather than the smallest, that is, signal transitions occur as fast as the timing constraints and the response of the environment will permit. Since interface adapters usually occur at the interface between modules it is expected that they will not be heavily replicated and their size will be amortized over the size of the entire design. 

For each interface operation JANUS checks for consistency among the diagrams. First, they must have the same basic block structure (conditionals and loops) with compatible entry conditions for each diagram segment. Second, label data items must be present on both sides and appear as inputs on one side and outputs on the other. Finally, after adding these data dependencies, the timing constraints must be checked to ensure no inconsistencies were introduced. For example, a violation would occur if two data dependencies caused a deadlock between the two interfaces. 

The behavioral specifrcation of a digital circuit consists of two parts its internal behavior (data-flow and operations) and its interface behavior (signaling conventions and their timing constraints). High-level synthesis systems use data-flow graphs to represent internal bdiavior. Event graphs are used to address the special nature of interface behavitv. 

In the early days of trace element spedation studies using chromatography coupled with ICP-MS, researchers had no choice but to interface their own LC pumps, columns, and autosamplers, etc., to the ICP mass spectrometer, because off-the-shelf systems were not commercially available. However, the analytical objectives of a research project are a little different from the requirements for routine analysis. With a research project, there are fewer time constraints to optimize the chromatography and detection parameters, whereas in a commercial environment, there are often financial penalties if the laboratory cannot be up, running real samples and... 

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