High-K dielectric layers

For application as a high-K dielectric layer for nansocale CMOS usable for future high-performance retina microchips, it is necessary to understand the TiAlOx/Si interface to reduce the density of charge-trapping states at that interface, which is currently the main limitation for insertion into a commercial CMOS device. 

AudeUo O, Fan W, Kabius B et al. (2005) New TiAl alloy high-K dielectric layer for next generation integrated circuit gates. Appl Phys Lett 86 1. 

Thangadurai, R Kaplan, W. D. Mikhelasbvili, V Eisenstien, G. 2009. The influence of electron-beam irradiation on electrical characteristics of metal-insulator-semiconductor capacitors based on a high-k dielectric stack of HfTiSiO(N) and HfTiO(N) layers. Microelectronics Reliability, 49(7) 716-720. 

Nishikawa T, Otsuka T, Moiita K (2002) Reduction of leakage current by Hf02 high K dielectric film stacked on the ferroelectric layer of a MFIS structure. Integr Ferroelectr 48(1) 41. 

Other component reliability issues related to lead-free solders include flip chips and wafer level CSPs with lead-free solder bumps and balls, where the higher soldering temperature and higher stiffness of the lead-free solder can adversely effect the reliability of the low-k dielectric layer on the die. Low k dielectric is needed for high speed applications, but is typically more fragile and prone to cracking. 

Two-dimensional numerical simulations of a 1.2-kV 4H-SiC UMOSFET with a 600-A layer of HfO as gate dielectric confirmed the benefits of using high-k gate dielectric in SiC UMOS transistors. Figure 5.3 shows electric field distribution in... 

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