Hardware design modelling

Argonne National Laboratory, (ANL) is pursuing fuel processor technology development that ranges from catalyst development, to component (CO, S cleanup, etc.) evaluations, to fuel processor hardware design, modeling, and demonstration. 

In order to reduce costs and increase the flexibility of HCS readers, it is to be expected that academic laboratories will assemble automated microscopes themselves. Hopefully this will be done with the Open Source hardware (OSHW) model, allowing other laboratories to reproduce the design (http //www.open-hardware.org) (15, 16). 

KINPTR is an overall process model thus it simulates all important aspects of the process which affect performance. In order to lay a foundation for upcoming discussions related to KINPTR development, the important aspects of naphtha reforming—chemistry, catalysis, and reactor/hardware design—will be summarized. More extensive reviews are available in the literature (1-3). 

Most of the published literature on reactive distillation (RD) has been focussed mainly on aspects such as conceptual design with the aid of residue curve maps, steady-state multiplicity and bifurcations, and development of equilibrium (EQ) stage and rigorous non-equilibrium (NEQ) steady-state and dynamic models [1, 2]. Relatively little attention has been paid to hardware design. In this chapter the concepts underlying the selection of the appropriate hardware for RD columns are discussed. For RD column design, detailed information on hydrodynamics and mass transfer for the chosen hardware is required, but this information is often lacking. Modern tools such as computational fluid dynamics (CFD) can be invaluable aids in hydrodynamic and mass-transfer studies. 

VHSIC Hardware Description Language (VHDL) is a widely used hardware description language which has become a standard in many domsuns. A common traditional use of VHDL has been to construct VHDL descriptions modeling the hardware design and then simulate the VHDL program to show that it meets a set of informal specification criteria from which test vectors have been generated. However, this approach is often insufficient in critical applications where it is desirable to prove that the VHDL description meets a set of formally specified correctness criteria, and a formal semantics of VHDL is thus needed. 

Encrenaz, E. (1995) A Symbolic Relation for a Subset of VHDL 87 Descriptions and its Application to Symbolic Model Checking. Correct Hardware Design and Verification Methods 95, 328-342. 

We can now apply the above model-checking t proach to asynchronous hardware designs, checking that they have the required behaviour, expressed as a CTL formula, and that they do not suffer from problems such as deadlock. We first oudine the Rainbow framework for giving compact design representations, and then illustrate how this can lead to a reduction in the size of model generated. 

SASSUR is targeted at bringing together experts, researchers, and practitioners from diverse communities, such as safety and security engineering, certification processes, model-based technologies, software and hardware design, safety-critical systems, and applications communities (railway, aerospace, automotive, health, industrial manufacturing, etc.). 

As shown above, formal approaches have some demonstrated successes in hardware design however, the essence of formal methods is that they require a perfect model of the physical system. Thus, due to the complexity of actual systems, formal approaches can be only used in parts of the design process. Typically, formal methods are used early in the development life cycle substituting formal abstraction for a complete physical model. Subsequent refinement is then used to map forward requirements to the later stages of the life cycle. 

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