Hardware Description HardwareC

Three hardware description languages were of particular interest as input languages in the Ascis project Silage, HardwareC, and Vhdl. 

A hardware description language called HardwareC was devel( )ed to capture the three requirements listed above. HardwareC is the input language to the Hercules and Hebe high-level synthesis system that is the system implementation of algorithms developed in this research ... 

Hardware description. The BE)CT chip was described in HardwareC and automatically synthesized by Hercules The design consists of a set of concurrent processes that communicate through a shared medium (Memory module in Figure 11.4). The shared memory is not described in HardwareC, but instead is mapped by a module generator directly to layout. Each MDCT module is described as two concurrent processes (phase-A and phase-B). Process phase-A computes the additions (IS) and subtractions (16) in parallel. The output of process phase-A is fed to process phase-B which performs the serial multiplications in parallel. The description of the two MDCT modules is identical except for the computation parameters. A full description of the MDCT in HardwareC is reported in [RM88]. The circuit was simulated at the functional and circuit level using Lsim [Sys88]. 

HardwareC supports two categories of design constraints timing and resource constraints. Timing constraints define upper and lower bounds on the time separation between operations. Resource constraints specify the number of resource components available, and partially bind calls to specific instances in the hardware implementation. The designer can also imbed arbitrary constraints in the description. This capability allows the designer to convey information that may be used by later synthesis steps. 

Behavioral transformations identify the parallelism in the HardwareC description using compiler optimization techniques. They also permit the designer to change the procedure calling hierarchy to conux)l the granularity of hardware sharing in subsequent synthesis steps. The BIF is used as the underlying representation for all transformations. 

Synthesis results. The ECC was synthesized and mapped to cells in LSI Logic s LCAIOK library. Two experiments were performed to illustrate the effect of resource sharing. In the first experiment, the hardware resources implementing PARITY.3 and PARITY-4 were assumed to have small area cost. This assumption corresponds to the actual implementation of these resources based on their HardwareC description, e.g. PARITY 3 is a three bit XOR and PARITY-4 is a four bit XOR. In the second experiment, the area cost for these resources was increased ten-fold to demonstrate the case where the area reduction due to sharing resources outweighs the area increase due to multiplexers and latching registers. Synthesis results of these experiments are summarized in Table 11.9. 

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