Fault Tolerance Techniques for Processors

The book is organized as follows Chap. 2 presents the terminology and general concepts used in this work. Chapter 3 describes existing fault tolerant techniques for processors presented in the literature. Chapter 4 describes the fault tolerant techniques implemented in this work to detect transierrt fairlts in processors, from which two are known software-based and three are new lybrid techniques. Chapter 5 presents experimental fault injection campaigns for the implemented fairlt tolerarrt techniques. Chapter 6 presents the configuration bitstream fairlt injection campaign and results. Chapter 7 presents radiation experiments on some of the proposed techniques. Chapter 8 describes future work and concludes the book. 

As the technology improves, new processor architectures arise. The literature in fault tolerance techniques for processor systems usuaUy tests their proposed techniques with sets of benchmarks. We intend to expand our case-study applications to a wider range, including real time and more applications, such as operating systems. 

The second novel hybrid fault tolerance technique. On-line Control Flow Checker Module (OCFCM) technique, was initially based on checkers, watchdog processors, and on the reconfigurability offered by modem FPGAs. It addresses recon-figurable systems with hardcore processors, such as FPGAs with embedded processors (for example, the Virtex Pro and Excalibur families, from Xilinx and Altera, respectively) or closed IP processors, such as the Microblaze from Xilinx. It can also be applied to ASICs, but with a few restrictions. 

This paper addresses some of the problems involved in the design of software for distributed processors, particularly where there are implications for safety. Modern software engineering techniques and languages are used to consider possible approaches to the design of such systems, and to discuss methods of providing fault tolerant structures for high reliability applications. 

Software-implemented fault tolerance is the most common TMR technique in use. This method involves three processors that nm asynchronously. This guards against transient errors. Each processor waits for the other two to cast their vote at certain points in the program cycle (at least once per input/output scan). The processors vote about ... 

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