Etching unit processes

These processes are considerably more complex in actual CMOS fabrication. First, the lower layers of a CMOS stmcture typically have a twin-tub design which includes both PMOS and NMOS devices adjacent to each other (see Fig. 3b). After step 1, a mask is opened such that a wide area is implanted to form the -weU, followed by a similar procedure to create the -weU. Isolation between active areas is commonly provided by local oxidation of sihcon (LOCOS), which creates a thick field oxide. A narrow strip of lightly doped drain (LDD) is formed under the edges of the gate to prevent hot-carrier induced instabiUties. Passivation sidewalls are used as etch resists. A complete sequence of fabrication from wafer to packaged unit is shown in Figure 10. 

The next step is to connect the individual unit operations in a block diagram, creating a process flow sheet. Figure 1 is an example of a simplified process flow diagram for a pattem-etch process for a printed wiring-board operation. There are... 

MECER A process for recovering copper from waste streams by extraction with a (s-diketone solution. Used in Germany, Sweden, the United Kingdom, and the USSR for treating effluent from the etching of printed circuit boards. 

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