Dual inlaid

Figure 9b Leahagee (log ampe.) at upper level metal (Cu dual inlaid) on a typical lot... 

We have demonstrated a successful six-level build after optimizing the unit TEOS, W, and Cu/barrier CMP processes. Within specification electrical parameters and repeatability of the process results were shown to be adequate for the dual inlaid logic and SRAM structures. Tool parameters, consumable changes, and endpoint algorithms were identified as key in the TEOS, W, and Cu/barrier CMP processes studied. 

Bell CG, HoweU PD, Stone HA (2013) Time-dependent chronoamperometric response of dual inlaid disk electrodes. J Electroanal Chem 689 303-313... 

The ideal deposition process would leave a perfectly flat surface. That does not happen, so a planarization process is required to maintain depth of field requirements. For a dielectric planarization process, the ideal planarization process would remove only material in the up areas and remove no material in the down areas. Metal CMP involves the removal of metal overburden, leaving filled plugs or vias (single damascene) or filled vias and inlaid metal lines (dual damascene) with no removal of metal in the inlaid region and no removal of dielectric. 

In addition, several issues arise with the use of either RIE etch back or CMP to remove the metal from on top of ILD. Dual layw inlaid metal schemes have been demonstrated for tungsten, aluminum, copper,and gold metallization systems. 

The name damascene derives from a technique of making inlaid metals that originated in ancient Damascus, now in present day Syria. See, for example, P. Singer, Making the move to dual damascene processing, Semiconductor Int, pp. 70 82 (Jan. 1999). 

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