DRAM Integration for Bandwidth-Demanding Applications

It can be observed from Fig. 7.3 that the requirement for peak memory bandwidth for NVidia GPUs has increased from 0.53 GB/s to 35.2 GB/s, or a factor of 66.7, in a period of 10 years beginning from 1994 (NVidia introduced its first GPU, NV1, in 1994). This momentum has to be continued with the adoption of advanced graphic features such as the 128-bit floating-point color depth and DVD quality real-time computer games. 

Although it already demonstrates many key advantages, the SCSP memory is of course not a fully 2.5-D integrated system yet. Most of all, the inter-chip 

It turns out that the 2.5-D regime is an ideal solution for a tiled multiprocessing architecture. The logic tile can be mapped to a high-performance CMOS chip and DRAM tiles can be allocated to a dedicated DRAM chip. The interface between logic and DRAM can be through inter-chip interconnects. With memory chips 

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