Doping, polysilicon layers

A phosphorus-doped polysilicon layer was used as the sensor heater. Its temperature coefficient of resistivity was positive with a value of 6 x 10 4°C 1. The value of the heater resistance as a function of temperature was used to indicate the sensor temperature. 

Table 17.2 and in Fig. 17.7 is suggested. The ways in which the chemistry influences the properties of doped polysilicon layers is discussed in the next section. 

Figure 4.2 Schematic diagram of a charge-coupled device (CCD) imaging sensor. It consists of a semiconducting substrate (silicon), topped by a conducting material (doped polysilicon), separated by an insulating layer of silicon dioxide. By applying charge to the polysilicon electrodes, a localized potential well is formed, which traps the charge created by the incident light as it enters the silicon substrate.

A schematic view of the cold cathode fabrication process is shown in Fig. 10.18. The cold cathode is fabricated by low pressure chemical vapor deposition (LPCVD) of 1.5 pm of non-doped polysilicon on a silicon wafer or a metallized glass substrate. The topmost micrometer of polysilicon is then anodized (10 mA cnT2, 30 s) in ethanoic HF under illumination. This results in a porous layer with inclusions of larger silicon crystallites, due to faster pore formation along grain boundaries. After anodization the porous layer is oxidized (700 °C, 60 min) and a semi-transparent (10 nm) gold film is deposited as a top electrode. 

A 1 ym thick polycrystalline silicon (polysilicon) layer was then deposited by chemical vapor deposition (CVD). Phosphorus doping of polysilicon was done by ion implantation with a dosage of 1Cr° cm-2 and a voltage of 200 keV. The polysilicon sheet resistance of 50 SI/ was obtained after post-implant activation (Figure 1a). 

The TEOS process just described has potential for use as an interlayer dielectric over metal layers that can withstand the high deposition temperature (i.e., doped polysilicon). If we want to cover aluminum, this process cannot be used. An alternative is to use a process where diacetoxyditertiarybutoxy-silane (DADBS)-(AcO)2Si(OtBu)2 will decompose at temperatures between 450° and 600°C.8... 

Second barrier layer (Si3N4) + DT fill with highly doped polysilicon + planarization by CMP (chemical mechanical polishing) + oxide collar recess as usual. 

Dopant species can be codeposited with the Si02 by introducing small amounts of the dopants in hydride or halide form. P-doped Si02, called P-glass, functions as an insulator between polysilicon gates and the top metallization layer of ICs. It is also used as a final passivation layer over devices, and as a gettering source (17). 

In Section 17.3.2(i) we have indicated a range of uses for polysilicon. For all of these applications there is a need to control layer structure. In addition, careful control of doping levels is also necessary. This can be done with post-deposition doping but this requires a high temperature (typically >900°C) in order to move the dopant atoms from the surface and to drive them into the layer. This high temperature diffusion step can cause thermal damage. One solution is to use in situ doping at the normal temperature of polysilicon deposition i.e., ca. 600°C. 

The integrated thermopile (1.6x10 mm) was manufactured by the following method. A quartz chip (25.2 x 14.8 x 0.6 mm) was used as a substrate instead of a silicon wafer, in order to reduce the heat conductivity of the chip. A 0.5 jim thick layer of polysilicon was deposited using LPCVD (low-pressure chemical vapour deposition) onto the quartz substrate. The layer was boron-doped using... 

---