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Design testing and verification

Finally, a timing simulation needs to be performed when the technology net-list has been placed and routed and the timing information is back-annotated to the design to include wiring delays. [Pg.13]

Fault simulators are a means of determining the behaviour of circuits when a fault occurs. They can be used to determine which parts of the circuit are [Pg.13]

Fault simulation occurs usually after most of the timing simulation is completed. At this stage test vectors can be generated and evaluated. Where certain parts of the circuit are difficult to test it may be necessary to redesign the circuit or reapply the test synthesis tools if they are used. [Pg.14]


See other pages where Design testing and verification is mentioned: [Pg.235]    [Pg.13]    [Pg.13]   


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