Design Rule Constraints DRC

The three design rule constraints are max fanout, max transition and max capacitance. In this section, we introduce these terms and the related dc shell conunands to specify these constraints. 

Instead, if the library has a default fanoutJoad attribute specified in the technology library, one can find this value using the following command  

The max transition design rule constraint does not provide a direct control over the actual capacitance of nets. The max.capacitance design rule constraint was introduced to provide a means to Umit capacitance directly. This constraint behaves like the max.transition constraint, but the cost hmction is based on the total capacitance of the net instead of the transition time. The max capacitance constraint is fully independent, so one can use it in conjunction with max.transition. During compile, DC ensures that there are no max.capacitance violations, that is, the max.capacitance constraint on the output pin of a driving cell exceeds or equals the summation of the capacitance of the pins driven by this cell and the net capacitances. The max capacitance attribute can be specified on designs or ports, max.transition, max fanout and max.capacitance can be used to control buffering in a design. 

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Figure 4.1 shows the two types of synthesis constraints and the related dc shell commands. Optimization constraints are user specified constraints. The two optimization constraints are speed and area constraints. In other words, DC considers speed and area as the two criteria for optimization. In addition to optimization constraints, the synthesis tool is required to meet another set of constraints called Design Rule Constraints (DRC). DRC are constraints imposed upon the design by requirements specified in the target technology library. Thus, DRC have precedence over optimization constraints since DRCs have to be met in order to realize a functional design. 

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