Design For Testability

The most popular DFT technique in ASIC design is the Scan Design Technique. Scan techniques involve replacing sequential elements in the design with equivalent scan cells. There exist different styles of scan cells. Based on the scan style selected the design is required to meet certain design rules. The most commonly used scan style is the multiplexed flip flop. 

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I. Ghosh, N. Jha, S. Dey. A low overhead design for testability and test generation techniques for core-based systems. In Proc. IntT Testing Conf., No. 1997, pp. 50- 59. 

Lighthart, M.M., Aarts, E.H.L., and Beenker, F.P.M. 1986. Design for testability of PLAs using statistical cooling. Proceedings of the 23rd ACM/IEEE Design Automation Conference, pp. 339-345, June 29-July 2. 

This is just one example of how to make your system under test more testable, which is called Design for testability. 

Ad hoc design for testability consists of a set of simple design rules of the form Do this, don t do that, where this and that are often not motivated with reasons. For example, when designing a board with ICs that have preset or clear pins, a rule might read as follows ... 

Scan technique is the most widely used Design For Testability(DFT) technique, and more importantly, is supported by most test synthesis tools. Iliis technique involves replacing the sequential non-scan cells by scan cells of the desired scan style. This transformation enables the sequential scan cells to be connected as a shift register in the scan mode. Further, for ATPG each of these scan cells behave as a pseudo primaiy input as well as a pseudo primaiy output. In this section, we discuss four basic issues related to Test Synthesis using TC, namely. Scan methodology. Scan Style, Scan Insertion and ASIC Vendor issues. 

Jager R., 1984. A Systematic Approach to Designing for Testability. Proceedings Annual R M Symposium. 

Also for hardware, most practices required for the lower ASILs, like review of block diagrams and layout, prototype tests and environmental tests, should not be new to experienced developers. Design for testability (e.g. at end of production line) is also an issue. To work with itemized textual requirements for hardware also (as the colleagues from software development have been used to do for many years) may be a new practice for many hardware developers. 

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