Chemical vapor deposition electrical insulators

In addition to silicon and metals, a third important element being deposited as thin films is diamond (Celii and Butler, 1991 May, 2000). For many years, diamonds were synthesized by a high pressure/high temperature technique that produced bulk diamonds. More recently, the interest in diamonds has expanded to thin films. Diamond has a slew of properties that make it a desired material in thin-film form hardness, thermal conductivity, optical transparency, chemical resistance, electrical insulation, and susceptibility to doping. Thin film diamond is prepared using chemical vapor deposition, and we examine the process in some detail as a prototypical chemical vapor example. Despite its importance and the intensity of research focused on diamond chemical vapor deposition, there remains uncertainty about the exact mechanism. 

J.H. Park, Electrically Insulating Eilms Deposited on V-4% Cr-4% Ti by Reactive CVD, presented at Chemical Vapor Deposition Session. 12th Surface Modification Technologies Conference, held in Conjunction with Symp. of Matls Solutions at ASM International Conference, Chicago, 1998. 

Elemental boron is a light element with a density of 2.34 g/cm It has a high melting point (2080°C), is hard, brittle and is an electrical insulator (resistivity 1.8 x 10 pQcm at 20°C) [10]. The element is barely reactive at room temperature, however it reacts with almost every element at elevated temperature. Thus, the preparation of pure boron presents a challenge, since impurities are incorporated readily into the boron lattice [221]. Boron has been prepared by chemical vapor deposition as early as 1911, when Weintraub deposited elemental boron from a mixture of BCI3 and Hi onto a heated wire [222]. Today, the CVD of boron is used to prepare coatings (e.g., for the first wall in fusion reactors) as well as fibers. Boron can be prepared by the hydrogen... 

Graphene can be prepared using four different methods [183]. The first is chemical vapor deposition (CVD) and epitaxial growth, such as the decomposition of ethylene on nickel surfaces. The second is the micromechanical exfoliation of graphite. The third method is epitaxial growth on electrically insulating surfaces, such as SiC, and the fourth is the solution-based reduction of graphene oxide (Fig. 31.17). 

In TSV, vertical micro through holes (vias) are chemically etched, mechanically drilled or laser drilled in the silicon die at the wafer level, then made electrically conductive by plating or vapor depositing metal conductors. The sidewalls of the vias, however, must first be insulated from the silicon. A dielectric film overlaid with conductive metal may be applied to the sidewalls or the exposed silicon may first be oxidized to isolate it from subsequent metallization. Connections within the chips are generally made between bond pads on one face of the die to a land on the opposite side. 

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